Suppose a computer using direct mapped cache has 2^32 bytes of byte-addressable main memory and a cache size of 512 bytes, and each cache block contains 64 bytes. a. How many blocks of main memory are there? b. What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields?

Is it possible to define the concept of locality of reference and demonstrate its efficacy in enhancing memory access?

27. Consider a logical address space of 256 pages with a 4-KB page size, mapped onto a physical memory of 64 frames. a. How many bits are required in the logical address? b. How many bits are required in the physical address?

4. The figure below shows an 8-way interleaved, byte-addressable memory. The total size of the memory is 4 KB. The elements A[i]G) of a 2-dimensional array A are 4-bytes (one-word) in length and can be stored in the memory as shown, where 0 < ij <7. The width of the bus between CPU and memory is 32 bits, that is, it can carry only one word at a time. Bank 1 Bank 7 Bank 0 31 7 A[7][0] A[I][0] A[0]|0] 32 A[7]1] 64 A[7]|2] A[I][2] A[0||2] RANKO 255 224 AI기기 A[I][7] A[0||7) RANKN ...... Since the address space of the memory is 4 KB, 12 bits are needed to uniquely identify each memory location, i.e., Addr[11:0]. Find out and explain which bits of the address will be used for: • Byte on bus: Addr […... :...] Bank index bits within a bank: Addr [.... .] • Chip select address bits within a rank: Addr […... .] • Rank bits: Addr […... :....]

Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. How many bits are used for the page number? How many bits are used for the offset? 8 bits each. With this system, what’s the maximum number of pages that a process can have? 256 Suppose that each entry in the page table comprises 4 bytes (including the frame number, the valid bit, and miscellaneous “bookkeeping bits”). An OS uses an array to store the page table. What is the size of the page table? 1024 Bytes Furthermore, suppose the first 6 pages of a process map to frames 222 to 227 (as decimal numbers), and the last 5 pages of the process map to frames 1 to 5 (also decimal numbers). All other pages are invalid. Draw the page table, including the valid bit and the frame number. DONE Translate the following virtual addresses to physical addresses, and show how you obtain the answers. (Hint: You do not need to convert…

Suppose the RAM for a certain computer has 4M words, where each word is 16 bits long. What is the capacity of this memory expressed in bytes? If this RAM is byte addressable, how many bits must an address contain? If this RAM is word addressable, how many bits must an address contain?

4. Assume 32 bit memory addresses, which are byte addresses. You have a direct-mapped cache with a block size of 8 bytes, and a size of 128 blocks. How many bits will the index, block offset, and tag be? How many total bits are required for the cache, including the data?

An address space is specified by 24-bits and the corresponding memory space by 16-bits. (i) How many words are there in the address space? (ii) How many words are there in the memory space?

mcq question The Physical address of the String Destination Memory Reference is:       DS:DI, DS:SI, and DS:BX       SS:SP, and SS:BP       ES:DI only       ES:DI and ES:SI

Before we can store (save) or retrieve (load) data in and out of the main memory, we need to provide the memory address to the memory control unit. This address uniquely identifies one single location (word or record) of the memory. Suppose this address is placed in Memory Address Register (MAR) prior to each memory access. What is the size of MAR for a 4GB RAM? (RAM is byte- addressable and each word is 2 bytes). Show all the work.