There is a 128 byte, direct-mapped cache where each cache block contains 8 bytes on a 16bit processor with 216 addressable bytes of memory, and assume the cache is initially empty (the valid bits are all zero). Suppose we are accessing the memory locations in the order of 0x18, 0x32, 0x75, 0x98, 0x35, 0x27, 0x56, 0x4F What’s the hit ratio? How many blocks are replaced? How the cache looks like in its final state? List the final state with each valid entry represented as a record of (similar as you did in HW7 Prob. 5.3.6).

There is a 128 byte, direct-mapped cache where each cache block contains 8 bytes on a 16bit processor with 2¹⁶ addressable bytes of memory, and assume the cache is initially empty (the valid bits are all zero). Suppose we are accessing the memory locations in the order of 0x18, 0x32, 0x75, 0x98, 0x35,

0x27, 0x56, 0x4F

1. What’s the hit ratio?
2. How many blocks are replaced?
3. How the cache looks like in its final state? List the final state with each valid entry represented as a record of <index, tag, data> (similar as you did in HW7 Prob. 5.3.6).

By providing answers to question a, b, and c above, please sketch the cache table indicating how each entry gets changed when different addresses are referenced.