Using Verilog continuous assignments or VHDL signal assignments, write a description of the circuit specified by the following Boolean functions: Out_1=(A+B′)C′(C+D)Out_2=(C′D+BCD+CD′)(A′+B)Out_2= (AB+C)D+B′CWrite a testbench and simulate the circuit’s behavior.

Write a Boolean expression for a NOR gate. F(A, B) = Write the Boolean expression for a four-input NOR gate. F(A, B, C, D) = To implement a 1-bit adder, write a Boolean expression for the Carry function. CarryOut(A, B, C;) = Input: A, B Carry in: C 2 pts 2 pts 2 pts

Simplify the given Boolean function and design half and full adder according to given input symbols. S(x, y, z)                 =             XY’Z’+X’YZ’+XYZ+X’Y’Z = Z⊕ (X⊕Y)

Given Boolean function is :F= x y + x′ y′ + y′ za. Implement it with only OR & NOT gatesb. Implement it with only AND & NOT gates

Given the following logic circuit, a logic expression for the output function is: Z O F(x,y,z) = x.(z+y)+z.(z+y) OF(x,y,z) = (z+y).(x+z) O F(x,y,z) = x.z+x.y+z+z.y O F(x,y,z) = x.y+z O All of the above O None of the above F

Implement the diagram in part b and verify its function experimentally by constructing a truth table from the test data.