Write a Verilog code with testbench for 16-bit up/down counter with synchronous reset and synchronous up/down. If up/down is set the counter is up counter and if it is not set, the counter is a down counter. clock reset IIn/down

Your task is to write code to implement a two-tone siren using the QUTy. You must use one of the Waveform Outputs of TCA0 to drive the buzzer. The buzzer should always be driven with a 50% duty cycle signal.   Your siren must alternate between the following frequencies:     f1 = 2110 Hz with f1 active for t1 = 370 ms     f2 = 4960 Hz with f2 active for t2 = 630 ms   NOTE: Your programme must be interrupt driven. dc = 50% main() will call the init() function you write below and then drop into an infinite loop. The init() function you write MUST return to demonstrate your code is interrupt driven.   In addition to init(), you may write any code you wish in this file, including ISRs. // NOTe: make sure to use the buffered versions of the CMP/PER registers //! NOTE: DO not use _delay_ms or _delay_us, we want you to do the math //! yourself and make your program interrupt driven in this program the buzzer should play f1 hz for t1 time, then play f2 hz t2 time, and it's play again and…

Draw the schematic for a synchronous 3-digit up/down counter with T flip-flops, with an enable function. So there will be two control lines: En and DIR. When En = 0, the counter stops. When En = 1, the counter counts. DIR determines the counting direction. When DIR = 1, the counter counts upward. When DIR = 0, the counter counts downward. %3D

Write in RTL Verilog. Use a 4-bit RCA, four 2-1 MUX, and four D-type flip-flops to implement a 4-bit counter