Systems Architecture
7th Edition
ISBN: 9781305080195
Author: Stephen D. Burd
Publisher: Cengage Learning
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Suppose two CPU A and B have exactly the same circuits, but different clock
frequencies. Answer the following questions:
a) If the clock frequency of CPU A is 8MHz, how long is one clock cycle of CPU A?
b) If the CPU A can execute 0.4 million instructions per second on average, how long is
the average time to execute one instruction?
c) What is the average number of clock cycle to execute one instruction for CPU A?
d) The frequency of CPU B is 12MHz. What is the average number of instructions that
can be executed per second?
Suppose that every 18 months, new generations of CPUs add another core to the number that can be used. Three years from now, how much extra off-chip memory bandwidth will be needed for a CPU to keep up with the same level of per-core speed?
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Suppose two CPU A and B have exactly the same circuits, but different clock
frequencies. Answer the following questions:
a) If the clock frequency of CPU A is 8MHz, how long is one clock cycle of CPU A?
b) If the CPU A can execute 0.4 million instructions per second on average, how long is
the average time to execute one instruction?
c) What is the average number of clock cycle to execute one instruction for CPU A?
d) The frequency of CPU B is 12MHz. What is the average number of instructions that
can be executed per second?
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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?arrow_forwardHow does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?arrow_forwardProcessor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?arrow_forward
- Let's say that the number of cores that can be used increases by one with each new generation of CPUs that comes out every 18 months. What percentage of additional off-chip memory bandwidth will be required in three years for a central processing unit to maintain the same level of per-core performance as it does today?arrow_forwardLet's say that the number of cores that are included on each new generation of central processing units (CPUs) increases by a factor of two every 18 months. How much more off-chip memory bandwidth will be needed for a CPU that is launched in three years if the per-core performance is to remain the same?arrow_forwardAt a minimum, how many bits are needed in the MAR with each of the following memory sizes? A memory unit that is said to be 640 KB would actually contain how many memory cells? What about a memory of 512 MB? What about a memory of 2 GB? Explain what use read-only memory (ROM) serves in the design of a computer system. What type of information is kept in ROM, and how does that information originally get into the memory?arrow_forward
- Suppose that a 2M × 16 main memory is built using 256K × 8 RAM chips and that memory is word addressable.1. a) How many RAM chips are necessary?2. b) If we were accessing one full word, how many chips would be involved? 3. c) How many address bits are needed for each RAM chip?4. d) How many banks will this memory have?5. e) How many address bits are needed for all memory?6. f) If high-order interleaving is used, where would address 14 (which is E in hex) be located?7. g) Repeat exercise 9f for low-order interleaving.arrow_forwardLet's pretend that the number of available cores in CPUs increases by one with each new generation, about every 18 months. If we fast forward three years, how much off-chip memory bandwidth would a CPU require to maintain the same per-core speed?arrow_forwardOn a uniprocessor, portion A of program P consumes 24 seconds, while portion B consumes 822 seconds. On a parallel computer, moderately serial portion A speeds up 4 times, while perfectly parallel portion B speeds up by the number of processors. 1- What is the speedup of program P on 1,024 processors? _______ times 2- How many processors are required to achieve at least half the theoretical maximum possible speedup on P?arrow_forward
- Assume that every 18 months, the number of cores available on a new generation of CPUs is doubled. How much extra off-chip memory bandwidth will be required in three years to maintain the current level of per-core performance?arrow_forwardConsider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. a. Which processor has the highest performance expressed in instructions per second? b. If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions. c. We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the CPI. What clock rate should we have to get this time reduction?arrow_forward
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