What are combinational MOS logic circuits?

MOS stands for metal-oxide-semiconductor. The combinational logic circuit performs Boolean operations and the output is determined as the Boolean function of the input. They are the basic building blocks of all digital systems. In this article, various static and dynamic characteristics of combinational MOS logic circuits will be examined. We will see that in the design and analysis of MOS circuits, the basic principle used can be directly applied to the combinational logic circuits.

Types of MOS logic circuit

  •  P-type MOS or PMOS logic
  •  N-type MOS or NMOS logic
  • Depletion-load NMOS logic
  •  High-Density NMOS  or HMOS logic
  • Complementary MOS or CMOS logic
  • Bipolar MOS or BiMOS logic

PMOS and NMOS logic

In the case of PMOS logic circuits, they use p-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) to implement the logic gates and other digital types of circuits, whereas NMOS type logic circuit uses n-channel MOSFETs to implement the logic gates and other digital types of circuits. The n-channel MOSFETs can be made smaller than p-channel MOSFETs for devices of equal current driving capability. The holes present in p-channel MOSFET have lower mobility than the electrons of the n-channel MOSFETs. The p-channel MOSFET in a silicon substrate produces only one type of MOSFET that is cheaper and technically simpler. By creating an inversion layer in an n-type transistor body, the PMOS transistors operate. In PMOS transistors, the n-channel is created by applying a negative voltage to the gate terminal. The PMOS transistors have four modes of operations in general. The NMOS logic, that uses n-channel MOSFETs, was the driving principle in its design. Even when no switching takes place, the NMOS logic consumes power, unlike CMOS logic, neglecting all the leakage current. Initially, NMOS was much faster than CMOS thus NMOS was much widely used for computers in the 1970s. With the advancement in technology, CMOS logic became the preferred process for digital chips after replacing NMOS logic in the mid-1980s.

Complementary MOS logic or CMOS logic

N-channel and P-channel field-effect transistors are used for CMOS circuits logic gates. CMOS circuits use oxide isolated metal CMOS gate. An NMOS pulldown the network and a PMOS pull up the network connected to output 1 is what a CMOS gate consists of. In the static state, CMOS uses no power in contrast to TTL. Other than leakage current a CMOS gate draws no current in a steady 1 or 0 state. To charge the capacitance current is drawn from the power supply when the gate switches state at the output of the gate. With the increase in switching rate, the current drawn by the CMOS devices increased. In 1968 by RCA as CD4000 COS/MOS, the 4000 series of the first CMOS family of logic integrated circuits was introduced. Initially, the then LS-TTL CMOS logic was slower. With simpler supplies, the CMOS devices were well adapted to battery-operated systems because the logic thresholds of CMOS were proportional to the voltage of the power supply. Because the logic thresholds are proportional to the power supply voltage, CMOS gates can also withstand much wider voltage ranges than TTL gates. The fixed levels are not required by the bipolar circuits. For implementing such digital CMOS functions the required silicon area has rapidly shrunk. CMOS is used by VLSI technology to incorporate millions of logic operations into one chip. By several orders of magnitude, the performance was increased by the very small capacitance of the on-chip wiring. On-chip clock rates have become common as high as 4 GHz that is 1000 times faster than the technology by 1970. NAND gate and NOR gate can be implemented using CMOS technology.

Lowering the power supply voltage

The other logic families of CMOS chips work with a broader range of voltages of the power supply. A power supply voltage of 5V was required earlier by TTL IC’s but the early CMOS could use 3 to 15 V. The charge stored in any of the capacitance and the energy required for logic transition are reduced by lowering the supply voltages. Reduced energy implies less heat dissipation. The energy stored in capacitance is given by 12CV2. Switching power is almost reduced by 60% by lowering the power supply from 5 V to 3.3 V. To provide even lower power supply voltages many motherboards have a voltage regulator module which is required by many CPUs.

CMOS inverter circuit
  CC BY-SA 3.0 | Image credit : https://en.m.wikipedia.org | Abaddon1337


HC logic

As the CD4000 series of the chips was incompatible with the previous TTL family, a new standard emerged that combined the best of the TTL family with the advantages of the CD4000 family. With devices that used 5 V power supplies and TTL logic levels, it was known as 74HC.

The CMOS-TTL logic level problem

Special techniques such as purpose-built interface circuits or additional pull-up resistors are required to interconnect any two logic families since the logic families may use different levels of voltage to represent 1 and 0 states and only met with the logic family may have other interface requirements. From those of CMOS, the TTL logic levels are different. To be reliably recognized by CMOS input as logic 1 the TTL output generally does not rise high enough. The invention of the 74HCT family resolved this problem because it uses CMOS technology but TTL input logic levels. These devices work with only a 5V power supply.  Although HCT is slower than the original TTL, they form a good replacement for TTL.

Other CMOS families

CMOS circuit families include pass transistor logic (PTL) and cascaded voltage switch logic (CVSL) of various sorts. They are not delivered as building block medium scale or small scale integrated circuits instead these are generally used “on-chip”.

Bipolar CMOS (BiCMOS) logic

To form a new type of logic device, a major improvement was to combine both the CMOS inputs and TTL drivers called BiCMOS logic. Among this family, the LVT, and ALVT logic families are the most important ones. ABT logic, ALVT logic, ALB logic, LVT logic, and BCT logic are the members of BiCMOS family.

Context and Applications

This topic is significant in the professional exam for Undergraduate, Graduate, and Postgraduate courses.

  • Bachelors of Technology (Electrical Engineering)
  • Bachelors of Technology (Electronics and Telecommunication)
  • Masters of Technology (Electrical Engineering)
  • Masters of Technology (Electronics and Telecommunication)

Practice Problems

Question 1: What does CMOS logic have in comparison to TTL?

  1. High speed of operation
  2. Higher power dissipation
  3. Smaller physical size
  4. None of the above


Explanation: The silicon area required for implementing CMOS is very small in size.

Question 2: Which gates can be implemented using CMOS technology?

  1. NAND gate
  2. NOR gate
  3. Both 1 and 2
  4. None


Explanation: NAND gate and NOR gate can be implemented using CMOS.

Question 3: Why PMOS is kept larger than the NMOS in size in the case of CMOS designs?

  1. To get higher drive strength
  2. To reduce power dissipation
  3. To get a balanced rise/fall time
  4. All of the above


Explanation: It is best if the rise and fall times of the output signal of the logic gates are the same to maximize the switching speed of a logic gate.

Question 4: What happens in the CMOS implementation of a NAND gate?

  1. All the PMOS and NMOS are in series.
  2. The two PMOS are in parallel and two NMOS are in series.
  3. All the PMOS and NMOS are in parallel.
  4. The two PMOS are in series and the two NMOS are in parallel.

Answer- b

Explanation: CMOS is a combination of NMOS and PMOS and the two PMOS are in parallel and the two NMOS are in series.  

Question 5: With what CMOS logic families are associated?

  1. Low power dissipation
  2. High noise immunity
  3. Comparatively high logic voltage swing.
  4. All of the above

Answer- a

Explanation: The CMOS devices have low power dissipation, high noise immunity, and comparatively high logic voltage swing.

  • Boolean algebra topics
  • Digital circuit
  • Combinational logic

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