What is a counter?

In digital logic and computing, a counter is a device that stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock. A sequential digital logic circuit is the most common type with an input line or clock and multiple output lines. In the binary or binary-coded decimal (BCD) number system, the values on the input line represents a number by several flip-flops connected in a cascaded manner. They are manufactured as separate integrated circuits and are widely used components in digital circuits. These are also a part of larger integrated circuits. These are a specific type of sequential circuit like registers or the value of the flip-flops serving as the output.

Binary counter timing diagram
CC BY-SA 4.0 | Image Credit: https://en.wikipedia.org | Audriusa

Types of counters

  • Asynchronous counter (Ripple or serial counter): With the output of one flip-flop serving as the clock pulse, the input of the next flip-flop, is triggered at a time in the chain. The counter output state of the asynchronous counters is free from the clock signal. As different clock edge pulses supply the flip-flops, the counter output state might delay the production.
  • Synchronous counter (Parallel counter): It is the counter that triggers all the flip-flops simultaneously.
  • Up counter: This type of counter counts from zero to the maximum number of counts.
  • Down counter: This type of counter counts from the maximum value to zero value.
  • BCD counter: Before the counter recycles, the counter counts from 0000 to 1001.
  • Pre-settable counter: Either synchronously or asynchronously, the counter that can be preset to any starting count is called a pre-settable counter.
  • Ring counter: This counter is a type of shift register, where the output of the last flip-flops is connected back to the input of the first flip-flop. The two types of ring counters are straight ring counters and twisted ring counters.
  • Johnson counter: This counter shifts registers where the inverted output of the last flip-flops connects to the input of the first flip-flops.

Synchronous counter

With the ripple counters, there is always a problem. In the clock pin or CLK, the flop checks the input pin D whenever a new clock pulse comes in. It also sets itself up in such a way that it remembers the input value. The changes that occurs due to the initial clock pulse signal, the output stages of the flip-flops take time to respond. It is only due to the internal propagation delay, which occurs with the given flip-flops. There may be an internal propagation delay of 30 ns in a standard Transistor–transistor logic (TTL) flip-flop. The accumulative propagation delay at the highest-order output will be 120 ns if 4 flip-flops are joined to create a MOD-16 counter. Such huge delays can lead to timing problems if used in a high-precision synchronous counter system. The synchronous counters are created to avoid larger delays. Synchronous counters contain flip-flops whose clock input is driven by a common clock line at the same time. Output transition of each flip-flop occurs at the same time and this shows that. To give the desired count waveform, one must use some logic circuitry additionally between various flip-flop inputs and outputs.

For instance, the addition of two additional AND gates is required to create a 4-bit MOD-16 synchronous counter. In hold mode or toggle mode, the AND gates act to keep a flip-flop. The first flip flop is in the toggle mode during 0-1 count whereas the rest of all are held in hold mode. The first and second flip-flops are placed in toggle mode when it is time for a 2-4 count sequence whereas the last two are held in hold mode only. The first AND gate is enabled when it is time for 4-8 count allowing the third flip-flop to toggle. The second AND gate is enabled when it is time for the 8-15 counts allowing the last flip-flop to toggle. This is how a four-bit MOD 16 synchronous counter is created.

Synchronous up-down counter

The down counter counts from the 4-bit count 1111 to 4-bit count 0000 and then goes to 4-bit count 1111. Each flip-flop complements when the previous flip-flops are all zero if one inspects the count cycle. Similar to the up counter, the down counter can be implemented except that the AND gate input is taken from Q' instead of Q.

Asynchronous up-down counter

Both up and down counters must be able to do up-counting and down-counting in certain applications. Depending upon the status of the control signals, a 3-bit up-down counter counts UP or DOWN. The NAND network between FF0 and FF1 gates the non-inverted Q outputs of FF0 into the clock input of FF1 when the UP input is at 1 and the DOWN input is at 0 in 3-bit mode. Into the clock input of FF2, Q outputs of FF1 will be gated through the other NAND network and the counter will count UP. The inverted outputs of FF0 and FF1 are gated into the clock inputs of FF1 and FF2 when the control input UP is at 0 and DOWN is at 1. As input pulses are applied, the counter goes through the following sequences if the flip-flops are initially reset to 0's. Because of the additional propagation delay introduced by the NAND networks, an asynchronous up-down counter is slower than an up counter or a down counter.

Binary up-down counter

Through any given count sequence, a binary counter is capable of counting either in the UP direction or DOWN direction. It is sometimes necessary to count "down" from a pre-determined value to a zero value by allowing us to produce an output from counting "up" from zero and by the increment to some pre-settable value. In a binary or BCD counter, this type of counter is often referred to as DOWN counter. The count decrement is by 1 for each type of external clock pulse from some pre-settable value in binary or BCD counters. To select either the up or down mode, a four-bit binary counter has an additional input pin.

Context and Applications

This topic is significant in the professional exams for undergraduate and postgraduate courses, especially for

  • Bachelors of Technology in Electrical Engineering
  • Masters of Technology in Electrical Engineering

Practice Problems

1. What is the number of natural states in a 4-bit ripple counter?

  1. 4
  2. 8
  3. 16
  4. 32

Answer- c

Explanation: In an n-bit counter the total number of states is given by 2n. So, for a 4-bit counter, the total number of states will be 24 =16 states.

2. How is internal propagation delay removed?

  1. Ripple counter
  2. Ring counter
  3. Multiplexer
  4. Synchronous counter

Answer- d

Explanation: In a synchronous counter, the clock input is given to each flip-flop individually. So, the internal propagation delay is removed by using a synchronous counter.

3. What is the internal propagation delay in a TTL flip-flop?

  1. 30 ns
  2. 60 ns
  3. 90 ns
  4. 120 ns

Answer- a

Explanation: There is an internal propagation delay of 30 ns in a standard TTL flip-flop.

4. In which counter, at the same time, all the flip-flops are triggered?

  1. Synchronous counter
  2. Asynchronous counter
  3. Multiplexer
  4. Ring counter

Answer- a

Explanation: In synchronous type counters, all the flip-flops are triggered at the same time.

5. What does the down counter count?

  1. Maximum to zero value
  2. Zero value to maximum value
  3. Low-to-high
  4. Logic 0 to logic 1

Answer- a

Explanation: A down counter always counts from maximum value to zero value.

  • Time to digital converter
  • Asynchronous circuit
  • Synchronous circuit
  • Multiplexer

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