ECE668 Quiz4(Includes calculation)

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Florida Polytechnic University *

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Computer Science

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Feb 20, 2024

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@ N TF .l 69%@ E&C-ENG568_E&C- ENG668_144587_FA22- Computer Architectulre Fall 2022 | Moodle home / My courses / Unit3 / Quiz4 Started on State Completed on Time taken Points Grade Question 1 Correct 10.00 points out of 10.00 " Flag question Monday, October 17, 2022, 7:42 PM Finished Monday, October 17, 2022, 8:32 PM 49 mins 52 secs 70.00/100.00 7.00 out of 10.00 (70%) Which of the following statements are false for a 5 stage MIPS pipeline with stages: IF, ID, EX, MEM and WB?
Question 1 Correct 10.00 points out of 10.00 " Flag question Which of the following statements are false for a 5 stage MIPS pipeline with stages: IF, ID, EX, MEM and WB? Select one or more: a. Store operations are only 4 active (doing something useful) during the IF, ID, EX and WB stages b. ALU operations are only active (doing something useful) during the IF, ID, EX and WB stages. c. Load operations are only g active (doing something useful) during the IF, ID, EX and WB stages. d. Branch operations areonly v active (doing something useful) during the IF, ID, EX and WB stages. Your answer is correct. ALU operations do not require the memory access step (MEM) that Loads and Stores do. Load operations are active during all 5 stages. Store operations do not require the write-back step (WB) that Loads and ALU operations do. They do not move data into the register file.
acuve (going sometning useful) during the IF, ID, EX and WB stages b. ALU operations are only active (doing something useful) during the IF, ID, EX and WB stages. c. Load operations are only b active (doing something useful) during the IF, ID, EX and WB stages. d. Branch operations areonly v active (doing something useful) during the IF, ID, EX and WB stages. Your answer is correct. ALU operations do not require the memory access step (MEM) that Loads and Stores do. Load operations are active during all 5 stages. Store operations do not require the write-back step (WB) that Loads and ALU operations do. They do not move data into the register file. 'Storing' of data is done in the MEM step. Stores are also active in the EX stage, as are Loads; the calculation of which memory address to go to is done here. This calculation is needed because of the use of relative addressing. Also, Branch operations do not require the memory access step (MEM) or the write-back step (WB). After the EX stage, the branch condition is known and the target has been calculated, nothing further is required for branch instructions. The correct answers are: Store operations are only active (doing something useful) during the IF, ID, EX and WB stages, Load operations are only active (doing something useful) during the IF, ID, EX and WB stages., Branch operations are only active (doing something useful) during the IF, ID, EX and WB stages.
Question 2 Correct 10.00 points out of 10.00 ¥ Flag question Suppose a program that executes 500 instructions is run using a 7-stage pipeline. In running the program, 142 stall cycles are inserted due to data dependencies. Assuming that the clock period of unpipelined processor is 10% less than the pipelined processor, calculate the Speedup due to pipelining. Round your answer to two decimal places. Answer: 491 v We first calculate the Pipeline.Stall.CPI = 142/ 500. Next, Speedup = (Pipeline.Depth / (1+Pipeline.Stall.CP1))* (CycleTimeynpipelined / CycleTimepipelined) = (7/ (1 +142/500) * 0.900 The correct answer is: 4.91
Question 3 Incorrect 0.00 points out of 10.00 ¥ Remove flag Suppose you have two programs to execute. Program 1 consists of 28% (Load + Store) instructions, Program 2 consists of only 3% (Load + store) instructions. You have two Machine choices for each program. Machine 1 contains a 2GHz, 20 stage pipeline with a dual ported memory and Machine 2 contains a 2.15GHz, 20 stage pipeline, but has a single ported memory. Assume that the clock rates above are for the pipelined case and that the clock rate for the unpipelined case is 2.8GHz for both machines. Which machine is the best choice for each program?
Assume that the clock rates above are for the pipelined case and that the clock rate for the unpipelined case is 2.8GHz for both machines. Which machine is the best choice for each program? (Hint: Calculate the speedup for each machine with Program 1 and 2 and compare). Select one: a. The best machine for Program 1 is Machine 2 and the best machine for Program 2 is also Machine 2. b. The best machine for Program 1 is Machine 1 and the best machine for Program 2 is Machine 2. c. The best machine for Program 1 is Machine 1 and the best machine for Program 2 is also Machine 1. d. The best machine for Program % 1 is Machine 2 and the best machine for Program 2 is Machine 1. Your answer is incorrect. First calculate the speedup for each machine N L Il S A SN I gn S
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