COMP 620 Homework#2

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California State University, Northridge *

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620

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Computer Science

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Oct 30, 2023

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Homework #2, 14-Multiple Choice Questions and 5-Essay Type Questions Deadline: Due by 11:59 p.m., October 11. 2023. Please Answer all Questions in BLUE color if applicable 1. For cache memory, locality is traditionally exploited by keeping recently used instruction and data values in cache memory and by exploiting a cache hierarchy. A. sequential B. direct access C. reference D. temporal 2. __________ is a random access type of memory that enables one to make a comparison of desired bit locations within a word for a specified match, and to do this for all words simultaneously. A. Direct access B. Associative access C. Unified cache D. Execution logic 3. For random access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use. A. access time B. memory cycle time C. transfer rate D. performance 4. For main memory, is the number of bits read out of or written into memory at a time. A. addressable units B. capacity C. unit of transfer D. direct unit 5. is a design principle which means that copies of the same data unit in adjacent memory levels must be consistent. A. Locality B. Coherence C. Inclusion D. Static 6. The cache is slower and typically larger than the L2 cache.

A. L1 B. L2 C. L3 D. L4 7. is the minimum unit of transfer between cache and main memory. A. Frame B. Tag C. Block D. Line 8. The principal disadvantage of mapping is the complex circuitry required to examine the tags of all cache lines in parallel. A. set-associative B. associative C. stack mapping D. direct 9. The __________ replacement algorithm replaces the block in the set that has been in the cache longest with no reference to it. A. LRU B. CLM C. FIFO D. LFU 10. The _________ replacement algorithm replaces the block in the set that has been in the cache longest. A. LFU B. LCA C. FIFO D. LRU 11. The __________ policy dictates that a piece of data in one cache is guaranteed to be also found in all lower levels of caches. A. noninclusive B. write allocate C. inclusive D. exclusive 12. The __________ policy dictates that a piece of data in one cache is guaranteed not to be found in all lower levels of caches.

A. write allocate B. exclusive C. write through D. inclusive 13. __________ can be caused by harsh environmental abuse, manufacturing defects, and wear. A. SEC errors B. Hard errors C. Syndrome errors D. Soft errors 14. _________ can be caused by power supply problems or alpha particles. A. Soft errors B. AGT errors C. Hard errors D. SEC errors Question 15: On the Motorola 68020 microprocessor, cache access takes two clock cycles. Data access from the main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a) Calculate the effective length of a memory cycle given a hit ratio of 0.9 . (i.e., one clock cycle equals 60 ns.) b) Repeat the calculation assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the result in terms of performance and average access time? Solution : Given, One Clock Cycle = 60ns Cache Access Takes 2 clock cycles = 2*60= 120ns Data access from the main memory over the bus to the processor takes 3 clock cycles Therefore, Memory Access Time = 3*60 = 180ns a) Effective Length of Memory Cycle = (Hit Ratio * Cache Access) + (Miss Rate * Main Memory Access Time) Given That, Hit Ratio = 0.9 So Miss Ratio Will be = 0.1 Effective Length of Memory Cycle = (0.9 * 120) + (0.1 * 180) = 108+ 18 = 126ns Therefore, Effective Length of Memory Cycle is 126ns

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b) Assume 2 wait states Clock Cycle = 2*60 = 120ns Cache Access Time = 2 Clock Cycle Main Memory Access Time = 3+2= 5 clock cycles= 5 * 60 = 300ns Effective length of Memory Cycle = (Hit ratio * Cache Access time) + (1-Hit Ratio) * Main Memory = 0.9 * 120 + (1- 0.9) * 300 = 108 + 30 Effective length of Memory Cycle = 138ns In Conclusion we can say that, By inserting wait states the average access time increases which degrades performance. Question 16: Consider a single-level cache with an access time of 2.5 ns, a block size of 64 bytes, and a hit ratio of H = 0.95. Main memory uses a block transfer capability that has a first word (4 bytes) access time of 50 ns and an access time of 5 ns for each word thereafter. a. What is the access time when there is a cache miss? Assume that the cache waits until the line has been fetched from main memory and then re-executes for a hit. b. What is the average memory access time? c. Suppose that increasing the line size to 128 bytes increases the H to 0.97. Does this reduce the average memory access time? Solution: Given That, Single level cache with the access time = 2.5ns Block Size = 64bytes = Line Size Hit Ratio = 0.95 Word Size = 4bytes Cache Size = Cache Line Size / Word Size = 64/4 Cache Size = 16 Bytes The block transfer capacity of main memory for first word = 50 ns The block transfer capacity of main memory for remaining words = 5 ns

a) To determine the access time when cache miss occurs: Tmiss = {Single Level cache with Access Time + 1 st block * block transfer capacity of 1 st word + 15 blocks * block transfer capacity of main memory for remaining words + time to read the requested word} Tmiss = 2.5 +50 * 1 + 15 *5 +2.5 Tmiss = 130ns Therefore the average access time when there is a cache miss is 130ns b) Average Memory Access Time = ( Hit ratio * Cache Memory Access Time) + (1 – Hit ratio) * Time required to access a block of main memory. Tmiss is considered as equivalent to quantity (T1 + T2) Average Access Time = (0.95 * 2.5) + (1-0.95) * 130 = 2.375 + 0.05*130 Average Access Time = 8.875ns c) Given suppose Line size increases to 128bytes and hit ratio increases to 0.97 Cache Size = Cache Line size / Word Size = 128 bytes/ 4 bytes Cache Size = 32 bytes Tmiss = { Single Level cache with Access Time + 1 st block * block transfer capacity of 1 st word + 15 blocks * block transfer capacity of main memory for remaining words + time to read the requested word} Tmiss = 2.5 + (50 * 1) + 32 * 5 + 2.5 = 52.5+162.5 Tmiss = 215ns

Therefore, Average Memory Access Time = Hit Ratio * T1+ (1-Hit Ratio) * Time required to access a block of main memory = 0.97 * 2.5 + (1-0.97) * (215) = 2.375 + 0.03*215 Average Memory Access Time = 8.825ns Increasing line size to 128 bytes doesn’t reduce the Average minimum access time Question 17: How many check bits are needed if the Hamming error correction code is used to detect single-bit errors in a 1024 -bit data word? Solution: 2 K – 1 ≥ M + K M =1024 2 k - 1 ≥ 1024+ k 2 k - k ≥ 1024 + 1 2 k - k ≥ 1025 If K= 10 2 10 – 1 ≥ 1024 +10 1024 - 1 ≥ 1034 1023 ≥ 1034 Not Satisfying If K = 11 2 11 – 1 ≥ 1024 +11 2048 - 1 ≥ 1035 2047 ≥ 1035 Therefore 11 Checkbits are needed

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Question 18: Consider a fully- associative cache with 8 cache blocks (numbered from 0 to 7) and the following sequence of memory block requests: 4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, 8, 3, 16, 25, 7 If LRU replacement policy is used, which cache block will have memory block 7 Solution: Time 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 1 5 1 6 17 Page # 4 3 25 8 19 6 2 5 8 16 35 45 22 8 3 1 6 2 5 7 Line 7 35 35 35 3 5 35 3 5 3 5 35 Line 6 16 16 16 16 1 6 16 1 6 1 6 16 Line 5 6 6 6 6 6 6 6 6 6 6 6 7 Line 4 19 19 1 9 1 9 19 19 19 19 1 9 3 3 3 3 Line 3 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Line 2 25 25 25 25 2 5 2 5 25 25 25 25 2 5 25 2 5 2 5 25 Line 1 3 3 3 3 3 3 3 3 3 3 22 2 2 22 2 2 2 2 22 Line 0 4 4 4 4 4 4 4 4 4 4 45 45 4 5 45 4 5 4 5 45 Hit/ Miss Mi ss Mi ss Mi ss Mi ss Mi ss Mi ss H it H it Mi ss Mi ss Mi ss Mi ss H it Mi ss H it H it Mi ss No.of Page Faults = 12 No.of Page Hits = 5 cache block number 5 will have memory block 7

Question 19: Based on a two-dimensional parity check, calculate the row and column parity bits for the given data set: 1010 0111 1100 0011 1001. At the receiver, the data has changed as below. How many errors can be detected by the two-dimensional parity check 1010 0111 1100 0010 0001. What would be the total redundancy? Solution: Original Data 1 0 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 0 1 1 1 Data To be sent 10100 01111 11000 00110 10010 10111 Receiver end 1 0 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 X 0 0 0 1 0 X 1 0 1 1 1 X X 2 errors , 2D parity Check 2 k - 1 ≥ M +K 2 k - 1 ≥ 20 +K 2 k ≥ 21 +K Let K= 4 2 4 ≥ 21+4 16 ≥ 25 Not True