final-2021-solution

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Computer Science

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Jan 9, 2024

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HONOR CODE I have not used any online resources during the exam. I have not obtained any help either from anyone in the class or outside when completing this exam. No sharing of notes/slides/textbook between students. NO SMARTPHONES. CANVAS ANSWERS MAY BE LOCKED AFTER 1ST TRY. Questions Sheet. Read all of the following information before starting the exam: For each question fill out the appropriate choice or write text on Canvas page. Also type clearly on in the exam on the appropriate text. IF THE MULTIPLE CHOICE ANSWER IS WRONG WE WILL MARK THE ANSWER WRONG. IF THE MULTIPLE-CHOICE ANSWER IS CORRECT, WE WILL READ THE WRITTEN PORTION. Show all work, clearly and in order, if you want to get full credit. I reserve the right to take off points if I cannot see how you logically got to the answer (even if your final answeris correct). Circle or otherwise indicate your final answers. Please keep your written answers brief; be clear and to the point. I will take points off for rambling and for incorrect or irrelevant statements. This test has six problems.

HONOR CODE Questions Sheet. Section Virtual Memory 17 points. Canvas Q1-Q31 Common questions. Canvas Q1-Q2 For the virtual address 0x11a39 answer the following Canvas Q3-Q12. (0.5 pt each) For the virtual address 0xab6e7 answer the following. Canvas Q13-Q22 (0.5 pt each) c. For the following virtual address 0x02974 answer the following (Canvas: 23-32) (0.5 pt each) B. Easy. RISCV Blackbox. [10 Points] 33. What is the value of the registers a0,a1, a2 on line 5: CHECK ? (show your working and explain your answer). Write down in hex [5] 34. Lets say message* is now a 2 character string "J-". The value of a2 on line 5:CHECK is 0. What is the mystery character "-". It has to be an ascii character between '0'--'9' (note not value 0-9). ? Write down the digit. [5] C. Lets Cache I (10pts) 35. What is the number of tag bits in Cache-A and Cache-B ? (1pt) 36. What is the number of index bits in Cache-A and Cache-B ? (1pt) 37. What is the number of offset bits in Cache-A and Cache-B ? (1pt) 38. What is the hit rate for Cache-A and Cache-B for loop 1? What types of misses do we get? (2 pts) 39. What is the hit rate for Cache-A and Cache-B when you execute loop 2? (5 pts) D. Lets Cache II (10pts) 40. What is the bits for virtual address? (1) 41. What is the bits for physical address? (1) 42. Which associativity below will maximize cache size while maintaining the same Tag:Index:Offset? (1) 43. Which block size below will maximize cache size while maintaining the same Tag:Index:Offset? (1) 44. Assuming associativity and block size from questions 42 and 43 what is the number of blocks? (1) 45. Now we’re working with a direct mapped cache with same TIO and block size as 43. What is miss rate for code below (3) 46. You add an L2 and shrink the L1. L1 hit latency is 3 cycles. L2 hit latency is 50 cycles. L2 hit rate is 90%. L1 hit rate is 25%. Memory is 100 cycles What is AMAT ? (2) F. RISC-V Single Cycle Datapath 47. What is the number of register that beqjalr needs to read and write in a single cycle ? (1) 48. What is the RegWEn signal ? (1) 49. What is the branch comparison signal we are interested in? (1) 50. Which fields are passed to the branch comparison ? (1) 51. What is the logic for beqjalr signal ? (1) 52. Consider the following modifications to the Reg[] register file. (2)

53. What are the inputs to the register file ? (2) 54. What are the inputs to the ALU ? (1) 55. What are the changes to mux-A ? (2) 56. What are the changes to mux-B ? (2) 57. For beqjalr instruction signal does WBsel choose ? (2) 58. What are the changes to the writeback stage ? (2) E. RISC-V Pipeline 12 points. 59. What hazards existing between instruction 1 and 2 ? (1) 60. What hazards existing between instruction 2 and 3 ? (1) 61. What hazards existing between instruction 3 and 4 ? (1) 62. What hazards existing between instruction 4 and 5 ? (1) 63. How many cycles does instruction 2 stall for ? (2) 64. How many cycles does instruction 3 stall for ? (2) 65. How many cycles does instruction 4 stall for ? (2) 66. How many cycles does instruction 5 stall for ? (2) G. Lets RISC-V II 10 points 67. We are designing a new RISC-V instruction with 16 registers. Assuming that you use the extra bits to extend the immediate field, what is the range of half-word instructions that can be reached using a branch instruction in this new format? (2) 66- refer code below 68. What is the PC address of instruction 4:beq (hex) ? 69. What is the PC address of instruction 9:addi (hex) ? 70. What is the PC address of instruction 12:ecall (hex) ? 71. What is the PC address of instruction 14:mul (hex) ? 72. What is the machine code for instruction at address 0x1C (hex) ? (2) 73. After the first pass of the assembler instruction at 0d20 does not have the label resolved. (1) 74. After the first pass of the assembler instruction at 0d28 does not have the label resolved. (1)

Section Virtual Memory 17 points. Canvas Q1-Q31 Refer slide deck L21-VM-III Week 8 if you need to. The chart below shows how memory accesses are treated in a system. The table below describes the parameters int he memory system. Please use the data below to answer question groups Q1,Q2,Q3,Q4 on canvas. CAUTION: When converting from binary to hex you can always pad the MSB e.g., 10 1010 (6 bit field) in hex is 0010 1010 (2 0s padded in MSB) is 0x2a . Parameter Value Physical address bits 16 Size of page 256 bytes Virtual address bits 20 ------------------------- --------------------- TLB Sets 4 TLB Ways 2 TLB Size 8 entries ----------------------- -------------------

Parameter Value Cache block 8 bytes Cache size 64 bytes Cache Sets 8 Cache Ways 1 Terminology VPN - Virtual page number Index (Set index of cache or TLB) PPN - Physical page number INVALID. TLB entry is invalid TLB-T (TLB Tag) TLB Way 0 PPN Index:0 TLB-T:[0x69] --- Index:1 TLB-T:[0x396] --- Index:2 TLB-T:[0x46] eb Index:3 TLB-T:[0x29c] 4a Way 1 0 Index:0 TLB-T:[0x3b] --- Index:1 TLB-T:[0x010] 88 Index:2 TLB-T:[0x2ad] 4b Index:3 TLB-T:[0x6] dc Page Table (Partial) CAUTION: Only partial table relevant to the questions are shown. VPN PPN Valid 0x1a4 --- 0

VPN PPN Valid 0xe59 --- 0 0x11a 0xeb 1 0xa73 0x4a 1 0xec 0x00 1 0x29 0x12 1 0xab6 0x4b 1 0x1b 0xdc 1 0x8ff 0x91 1 0xbf1 0x47 1 0x016 0x99 1 0x010 0x88 1

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