BJT Exploration 1_NPN DC Biasing and CE Amp Configurations (1)

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Feb 20, 2024

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BJT Exploration 1 NPN DC Biasing and Common-Emitter Amplifier Configurations: Part I: NPN DC Biasing Figure 1: NPN DC Bias Circuit 1. DC Bias Circuit Design: A. Design the NPN DC Bias Circuit of Figure 1 using a β → ∞ model for the transistor (i.e. assuming the base current is zero): Determine the values of R C and R E so that the transistor operates at I C = 1.1 mA and V C = + 0.7 V . Outline each step of your design process and summarize your results in Table 1. (Reference: See Example 6.9 in the Sedra and Smith textbook, 8 th ed.). Include in Table 1 the standard 5% tolerance resistor values that are closest to your design values. Table 1: NPN DC Bias Circuit Design R C R E Resistor value from design Closest Standard 5% tol. Resistor value
B. Design Validation with Multisim Live Simulation: In Multisim Live create the design of the circuit of Figure 1 using the closest standard 5% tolerance resistor values for of R C and R E and the generic Multisim NPN model component. Insert voltage probes at nodes C and E and perform a DC Op (DC Operating Point) simulation to determine the simulated values of V C and V E . Calculate the value of I C and complete Table 2 to compare the DC Bias Point specifications in 1. A to what was achieved in the simulated circuit. Table 2 Validation of DC Bias Circuit Design V C V E I C Design Specification 0.7 V 1.1 mA Design Validation from Simulation Part II: Common-Emitter Amplifier Configurations Figure 2: NPN Common-Emitter Amplifier with Emitter Resistor Degeneration Configurations 2. Theory: A. Common-Emitter Amplifier with Emitter Resistor R E Degeneration:
The NPN BJT amplifier of Figure 2 is configured as a Common-Emitter with Emitter Resistor Degeneration amplifier. With S2 Open, the total emitter resistance, R E = R E1 + R E2 , in the emitter branch provides a high level of DC bias stability to this design, however, when left un-bypassed it results in significant degeneration of the magnitude of the small-signal voltage gain, A v . The theoretical small-signal voltage gain of the Common-Emitter with Emitter Resistor Degeneration configuration under No Load (S1 Open) is given by: A v = v 0 v i = R C g m + R E Where = β 1 + β β→∞ 1 and the value of the small-signal transconductance depends on the DC bias point and is given as: g m = I C 25 mV B. Common-Emitter Amplifier with partial Emitter Resistor R E1 Degeneration: (S2 Closed) With S2 Closed, the R E2 part of R E is bypassed through capacitor C 3 removing it’s degeneration effect on the small-signal voltage gain. Since capacitors are open-circuits to DC, even with S2 Closed, the total emitter resistor R E still provides the desired DC bias stability to this design. Once R E2 is bypassed, the achievable value of the small-signal voltage gain, A v becomes much larger. The theoretical small-signal voltage gain of the Common-Emitter Configuration with R E1 ( R E2 bypassed) (S2 Closed) under No Load (S1 Open) becomes: A v = v 0 v i = R C g m + R E 1 Using the results of the Multisim Live simulated DC bias point of 1. B. and V tn = 2.2 V , calculate the theoretical values of g m and the voltage gains of (i) the Common-Source with Source Resistor Degeneration configuration under No Load (S1 Open) and (ii) the Common- Source configuration under No Load (S1 Open). Summarize your results in Table 3. Table 3 Small-signal Properties of NPN CE Amplifier Configurations Transistor transconductance, g m (mA/V) No load voltage gain of CE with R E Emitter Degeneration, (S2 Open) A v (V/V) No load voltage gain of CE with R E1 Emitter Degeneration, (S2 Closed) A v (V/V)
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