T10

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Swinburne University of Technology *

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EEE20001

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Electrical Engineering

Date

Oct 30, 2023

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pdf

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Uploaded by bercianoj

Digital Electronics - Tutorial 38 of 46 Tutorial 10 Solution Q1) Vending Machine (Not provided) Q2) 3-bit Up/Down counter with count enable (Updated to use ieee.numeric_std ) -------------------------------------------------------------------------------- -- Tutorial 10 Q2) 3-bit up/down counter module with count enable -------------------------------------------------------------------------------- library IEEE; use ieee.std_logic_1164. all ; use ieee.numeric_std. all ; entity count3 is Port ( reset : in std_logic ; clock : in std_logic ; countEn : in std_logic ; direction : in std_logic ; q : out std_logic_vector ( 2 downto 0 ) ); end entity count3; architecture Behavioral of count3 is signal tq : signed ( 2 downto 0 ); begin q <= std_logic_vector ( count ); -- Convert value to std_logic_vector sync: process ( reset , clock ) begin if ( reset = '1' ) then count <= ( others => '0' ); elsif (rising_edge( clock )) then if ( countEn = '1' ) then if ( direction = '1' ) then count <= count + "1" ; else count <= count - "1" ; end if ; end if ; end if ; end process sync; end architecture Behavioral;

Digital Electronics - Tutorial 39 of 46 3-bit Up/Down counter with count enable (Updated to use ieee.numeric_std ) -------------------------------------------------------------------------------- -- Tutorial 10 Q3) 3-bit ‘automatic’ up/down counter module with count enable -- Also a good example of using enumerated types outside of state machines -------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164. all ; use IEEE.numeric_std. all ; entity count3 is Port ( reset : in std_logic ; clock : in std_logic ; countEn : in std_logic ; q : out std_logic_vector ( 2 downto 0 ) ); end entity count3; architecture Behavioral of count3 is signal count : unsigned ( 2 downto 0 ); -- It is common to use unsigned for counters type DirectionType is ( up , down ); -- Example use of enumerated type signal direction : DirectionType ; -- Easier to 'read' begin q <= std_logic_vector ( count ); -- Convert value to slv for output sync : process ( reset , clock ) begin if ( reset = '1' ) then count <= ( others => '0' ); direction <= up ; elsif (rising_edge( clock )) then -- Note that assignments to direction and count both produce FFs if ( countEn = '1' ) then case direction is when up => count <= count + "1" ; when down => count <= count - "1" ; end case ; -- Change direction 1 clock early to allow for delayed action on following edge if ( count = "001" ) then direction <= up ; elsif ( count = "110" ) then direction <= down ; end if ; end if ; end if ; end process sync; end architecture Behavioral;

Digital Electronics - Tutorial 40 of 46 Q4) Example VHDL P1: process( reset, clock ) begin if (reset = '1') then x <= '0'; elsif (rising_edge(clock)) then x <= w; end if; end process P1; P2: process( clock ) begin if (rising_edge(clock)) then if (clear = '1') then x <= '0'; else x <= w; end if; end if; end process P2; Asynchronous Reset Synchronous Reset (Clear input)

T10

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