T9

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Swinburne University of Technology *

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EEE20001

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Electrical Engineering

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Oct 30, 2023

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pdf

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Uploaded by bercianoj

Digital Electronics - Tutorial 32 of 46 Tutorial 9 Solution Q1) P1 : process ( clock ) begin if rising_edge ( clock ) then t <= w or x ; b <= t and y ; end if ; end process P1 ; Note: Two FFs. The assigments to t and b are separated by a clock cycle! P2 : process ( clock , t , y ) begin if rising_edge ( clock ) then t <= w or x ; end if ; b <= t and y ; end process P2 ; Q2) --==================================================== -- Two example shift register architectures -- entity ShiftRegister is Port ( reset : in STD_LOGIC ; clock : in STD_LOGIC ; shiftEn : in STD_LOGIC ; loadEn : in STD_LOGIC ; serialIn : in STD_LOGIC ; d : in STD_LOGIC_VECTOR ( 7 downto 0 ); q : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); end ShiftRegister ;

Digital Electronics - Tutorial 33 of 46 Q2) cont. --================================================= -- 8-bit SR -- Asynchronous reset -- Asynchronous load -- Synchronous shift (obviously) architecture Behavioral of ShiftRegister is signal tq : STD_LOGIC_VECTOR ( 7 downto 0 ); begin q <= tq ; process ( reset , loadEn , d , clock ) begin if ( reset = ' 1 ' ) then -- asynchronous reset tq <= ( others => ' 0 ' ); elsif ( loadEn = ' 1 ' ) then -- asynchronous load tq <= d ; elsif rising_edge ( clock ) then if ( shiftEn = ' 1 ' ) then – - synchronous shift left tq <= tq ( 6 downto 0 ) & serialIn ; -- or tq <= tq(tq'left-1 downto tq'right) & serialIn; end if ; end if ; end process ; end Behavioral ; --================================================= -- 8-bit SR -- Asynchronous reset -- Synchronous load -- Synchronous shift (obviously) architecture Behavioral2 of ShiftRegister is signal tq : STD_LOGIC_VECTOR ( 7 downto 0 ); begin q <= tq ; process ( reset , clock ) begin if ( reset = ' 1 ' ) then -- asynchronous reset tq <= ( others => ' 0 ' ); elsif rising_edge ( clock ) then if ( loadEn = ' 1 ' ) then -- synchronous load tq <= d ; elsif ( shiftEn = ' 1 ' ) then -- synchronous shift left tq <= tq ( 6 downto 0 ) & serialIn ; -- or tq <= tq(tq'left-1 downto tq'right) & serialIn; end if ; end if ; end process ; end Behavioral2 ;

Digital Electronics - Tutorial 34 of 46 Q3) --=================================================================== -- dieCounter.vhdl -- -- A counter to produce a roll in the range 1 .. 6 (like a die) -- -- Revision History --=================================================================== -- 6/4/17 - Created - pgo --=================================================================== library ieee ; use ieee . std_logic_1164 . ALL ; use ieee . numeric_std . all ; entity dieCounter is Port ( reset : in std_logic ; clock : in std_logic ; roll : in std_logic ; count : out std_logic_vector ( 2 downto 0 ) ); end dieCounter ; architecture Behavioural of dieCounter is signal dieCount : unsigned ( 2 downto 0 ); begin count <= std_logic_vector ( dieCount ); -- Produce dieCount sequence from 1 ... 6 counter : process ( reset , clock ) begin if ( reset = ' 1 ' ) then dieCount <= "001" ; -- start count from 1 elsif ( clock' event and ( clock = ' 1 ' )) then if ( roll = ' 1 ' ) then -- rolling if ( dieCount >= "110" ) then dieCount <= "001" ; -- wrap count else dieCount <= dieCount + "001" ; end if ; end if ; end if ; end process ; end Behavioural ;

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