ECE 231 - Fall 2023 - HW1 - Solutions
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Course
231
Subject
Electrical Engineering
Date
Dec 6, 2023
Type
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Homework Assignment #1
Fall 2023
Homework #1
R
EADING
: 1. ZyBook: 1.1 – 1.5
M
ULTIPLE
C
HOICE
AND
S
HORT
-
ANSWER
Q
UESTIONS
: [½ point each] 1.
For which value of the noise margin (NM) will a logic circuit not
function properly?
(a) NM > 0 (positive)
(b) NM < 0 (negative)
(c) 0 < NM < 1
(d) All of the above.
(e) None of the above.
2.
For which value of the fan-out (FO) will a logic circuit not
function properly?
(a) FO > 0 (positive)
(b) FO < 0 (negative)
(c) FO = 0
(d) All of the above.
(e) None of the above.
4.
Where was the first point contact transistor constructed? (a) Marconi Company
(b) Texas Instruments
(c) RCA’s Research Lab
(d) Bell Labs
(e) Fairchild Semiconductor
5.
Which company demonstrated that transistors could be mass produced using silicon? (a) Texas Instruments
(b) Fairchild Semiconductor (c) Intel
(d) IBM
(e) Bell Labs
ECE 231 – Digital System Design
1 of 12
Dr. Craig Lorie
Homework Assignment #1
Fall 2023
6.
Who invented the integrated circuit?
(a) Steven Hofstein and Frederic Heiman
(b) Jack Kilby and Robert Noyce
(c) Gordon Teal
(d) Alan Cho
(e) William Shockley
7.
What is the value on the gate input of a pMOS transistor that causes it to be closed? (a) Logic-1 (i.e. the supply voltage, VDD)
(b) Logic-0 (i.e. ground, GND)
(c) Either logic-1 or logic-0
(d) The Gate input does not control the pMOS transistor. (e) None of the above.
8.
Which logic operation is implemented by the CMOS circuit given below?
(a) NAND
(b) NOR
(c) AND
(d) OR
(e) XOR ECE 231 – Digital System Design
2 of 12
Dr. Craig Lorie
Homework Assignment #1
Fall 2023
L
ONG
-A
NSWER
P
ROBLEMS
: [2 points each] 1.
Calculate the noise margin high (NM
H
) and noise margin low (NM
L
) for each pair of logic gates
specified below. Refer to the data sheets provided on Blackboard. The following values were taken from the datasheets for the 74LS04, 74HC04, and 74F04, that were provided with the homework assignment. These values were used in the calculations of noise margin
below. Please review the datasheets to confirm the values given below.
74LS04
74HC04
74F04
V
OH
2.7 V
4.4 V
2.5 V
V
OL
0.5 V
0.1 V
0.5 V
V
IH
2.0 V
3.15 V
2.0 V
V
IL
0.8 V
1.35 V
0.8 V
(a)
driver: 74F04
load:
74F04
NM
H
= V
OH
– V
IH
= 2.5 V – 2.0 V = 0.5 V NM
L
= V
IL
– V
OL
= 0.8 V – 0.5 V = 0.3 V
(b)
driver: 74F04
load:
74LS04 NM
H
= V
OH
– V
IH
= 2.5 V – 2.0 V = 0.5 V NM
L
= V
IL
– V
OL
= 0.8 V – 0.5 V = 0.3 V
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Homework Assignment #1
Fall 2023
(c)
driver: 74F04
load:
74HC04
NM
H
= V
OH
– V
IH
= 2.5 V – 3.15 V = – 0.65 V
NM
L
= V
IL
– V
OL
= 1.35 V – 0.5 V = 0.85 V
(d)
driver: 74LS04
load:
74F04
NM
H
= V
OH
– V
IH
= 2.7 V – 2.0 V = 0.7 V NM
L
= V
IL
– V
OL
= 0.8 V – 0.5 V = 0.3 V
(e)
driver: 74HC04
load:
74F04
NM
H
= V
OH
– V
IH
= 4.4 V – 2.0 V = 2.4 V NM
L
= V
IL
– V
OL
= 0.8 V – 0.1 V = 0.7 V
ECE 231 – Digital System Design
4 of 12
Dr. Craig Lorie
Homework Assignment #1
Fall 2023
2.
Calculate the fan-out high (FO
H
), fan-out low (FO
L
), and maximum fan-out (FO
MAX
) for each pair of logic gates specified below. Refer to the data sheets provided on Blackboard.
The following values were taken from the datasheets for the 74LS04, 74HC04, and 74F04, that were provided with the homework assignment. These values were used in the calculations of fan-out
below. Please review the datasheets to confirm the values given below.
74LS04
74HC04
74F04
I
OH
– 0.4 mA
– 20 °
A
– 1 mA
I
OL
8 mA
20 °
A
20 mA
I
IH
20 °
A
0.1 °
A
5 °
A
I
IL
– 0.36 mA
– 0.1 °
A
– 0.6 mA
(a)
driver: 74F04
load:
74F04
FO
H
= | I
OH
/ I
IH
| = | – 1 mA / 5 °
A | = 200
FO
L
= | I
OL
/ I
IL
| = | 20 mA / – 0.6 mA | = 33.33 = floor[33.33] = 33
FO
MAX
= min{ 200, 33 } = 33
Therefore, an “F” device can be connected to, at most, 33 “F” devices.
ECE 231 – Digital System Design
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Dr. Craig Lorie
Homework Assignment #1
Fall 2023
(b)
driver: 74F04
load:
74LS04 FO
H
= | I
OH
/ I
IH
| = | – 1 mA / 20 °
A | = 50
FO
L
= | I
OL
/ I
IL
| = | 20 mA / – 0.36 mA | = 55.55 = floor[55.55] = 55
FO
MAX
= min{ 50, 55 } = 50
Therefore, an “F” device can be connected to, at most, 50 “LS” devices.
(c)
driver: 74F04
load:
74HC04
FO
H
= | I
OH
/ I
IH
| = | – 1 mA / 0.1 °
A | = 10000
FO
L
= | I
OL
/ I
IL
| = | 20 mA / – 0.1 °
A | = 200000
FO
MAX
= min{ 10000, 200000 } = 10000
Therefore, an “F” device can be connected to, at most, 10000 “HC” devices.
(d)
driver: 74LS04
load:
74F04
FO
H
= | I
OH
/ I
IH
| = | – 0.4 mA / 5 °
A | = 80
FO
L
= | I
OL
/ I
IL
| = | 8 mA / – 0.6 mA | = 13.33 = floor[13.33] = 13
FO
MAX
= min{ 80, 13 } = 13
Therefore, an “LS” device can be connected to, at most, 13 “F” devices.
(e)
driver: 74HC04
load:
74F04
FO
H
= | I
OH
/ I
IH
| = | – 20 °
A / 5 °
A | = 4
FO
L
= | I
OL
/ I
IL
| = | 20 °
A / – 0.6 mA | = 0.033 = floor[0.033] = 0
FO
MAX
= min{ 1, 0 } = 0
Therefore, an “HC” device can be connected to, at most, 0 “F” devices.
That is, the “HC” device does not source/sink enough current for the “F” device.
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Homework Assignment #1
Fall 2023
3.
Which of the following driver-load
combinations will NOT work? Select ALL that apply.
Refer to problems 1 and 2 above.
Hint: you must consider both the noise margin and the fan-out.
(a)
driver: 74F04 load:
74F04
NM
H
= V
OH
– V
IH
= 2.5 V – 2.0 V = 0.5 V NM
L
= V
IL
– V
OL
= 0.8 V – 0.5 V = 0.3 V
FO
MAX
= min{ 50, 33 } = 33
(b)
driver: 74F04
load:
74LS04 NM
H
= V
OH
– V
IH
= 2.5 V – 2.0 V = 0.5 V NM
L
= V
IL
– V
OL
= 0.8 V – 0.5 V = 0.3 V
FO
MAX
= min{ 50, 50 } = 50
(c)
driver:
74F04
load:
74HC04
NM
H
= V
OH
– V
IH
= 2.5 V – 3.15 V = – 0.65 V NM
L
= V
IL
– V
OL
= 1.35 V – 0.5 V = 0.85 V
FO
MAX
= min{ 10000, 200000 } = 10000
(d)
driver: 74LS04 load:
74F04
NM
H
= V
OH
– V
IH
= 2.7 V – 2.0 V = 0.7 V NM
L
= V
IL
– V
OL
= 0.8 V – 0.5 V = 0.3 V
FO
MAX
= min{ 20, 13 } = 13
(e)
driver:
74HC04
load:
74F04
NM
H
= V
OH
– V
IH
= 4.4 V – 2.0 V = 2.4 V NM
L
= V
IL
– V
OL
= 0.8 V – 0.33 V = 0.47 V
FO
MAX
= min{ 1, 0 } = 0
ECE 231 – Digital System Design
7 of 12
Dr. Craig Lorie
Homework Assignment #1
Fall 2023
4.
Analyze the CMOS circuit given below. For each input combination specified in the table below:
•
Indicate the state of each transistor as either OP (open) or CL (closed).
•
Specify the logical value at the output as either 0 or 1.
A
B
C
D
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
F
(a)
1
0
0
1
OP
CL
CL
OP
CL
OP
OP
CL
0
(b)
1
0
0
0
OP
CL
CL
OP
CL
OP
CL
OP
1
(c)
1
1
0
1
OP
CL
OP
CL
CL
OP
OP
CL
0
(d)
0
0
1
0
CL
OP
CL
OP
OP
CL
CL
OP
0
(e)
0
1
0
0
CL
OP
OP
CL
CL
OP
CL
OP
1
ECE 231 – Digital System Design
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Dr. Craig Lorie
Homework Assignment #1
Fall 2023
P
RACTICE
P
ROBLEMS
: (Do not submit solutions to these problems) 1.
In what year was the integrated circuit (IC) invented?
1959
2.
Who invented the MOSFET? (Identify all persons involved).
Hofstein and Heiman
3.
At which company was the first point-contact transistor constructed?
Bell Labs
4.
What does Moore's Law state?
Moore's Law states that the number of transistors on a (very large scale) integrated circuit will double approximately every two years. With the doubling of the number of transistors,
it is expected that the performance of such integrated circuits (e.g. processors) will also double in the same time frame. This allows processor developers to predict the functionality and performance of future generations of their processors.
See “
http://www.mooreslaw.org/
”.
See “
http://en.wikipedia.org/wiki/Moore%27s_law
”
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Homework Assignment #1
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5.
A digital signal is discrete
in time and discrete
in magnitude. (Fill in the blanks).
A brief description of analog, digital, and binary signals:
Analog signal
An analog signal is one that is continuous in time and continuous in magnitude.
It has a valid value at all points in time.
It can take on any value between the specified minimum and maximum values.
Digital signal
A digital signal is one that is discrete in time and discontinuous in magnitude.
It has a valid value at all points in time, however, can transition between valid
values only at discrete points in time.
It can take on only a limited set of values between the specified minimum and
maximum values. The number of values, or steps, that a digital signal can take on determines the precision with which it can approximate an analog signal. Binary signal
A binary signal is a digital signal that is limited to just two values.
The two values of a binary signal are typically represented by 0 and 1.
6.
What are the advantages of using digital, rather than analog, circuits? (Identify two).
Provides improved noise immunity.
It’s more reliable.
It’s less expensive.
It’s programmable.
7.
In what applications can digital systems be found?
8.
Why do we use digital systems?
ECE 231 – Digital System Design
10 of 12
Dr. Craig Lorie
Homework Assignment #1
Fall 2023
9.
Analyze the CMOS circuit given below.
For each input combination (ABC = 000 through ABC = 111): •
Indicate the state of each transistor as either OP (open) or CL (closed).
•
Specify the logical value at the output as either 0 or 1.
Provide your answer in the form of a function table.
ECE 231 – Digital System Design
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Dr. Craig Lorie
Homework Assignment #1
Fall 2023
For the CMOS circuit above:
•
Input A is connected to Q1 (pMOS) and Q2 (nMOS). •
Input B is connected to Q3 (pMOS) and Q4 (nMOS).
•
Input C is connected to Q5 (pMOS) and Q6 (nMOS).
Therefore, for a given value of A, Q1 and Q2 will have opposite behaviors (i.e. when one is open
the other is closed
). A similar statement can be made for inputs B and C.
The function table for the CMOS circuit is given below.
A
B
C
Q1
Q2
Q3
Q4
Q5
Q6
F
0
0
0
closed
open
closed
open
closed
open
1
0
0
1
closed
open
closed
open
open
closed
1
0
1
0
closed
open
open
closed
closed
open
1
0
1
1
closed
open
open
closed
open
closed
1
1
0
0
open
closed
closed
open
closed
open
1
1
0
1
open
closed
closed
open
open
closed
1
1
1
0
open
closed
open
closed
closed
open
1
1
1
1
open
closed
open
closed
open
closed
0
As can be determined from the table, the CMOS circuit implements a 3-input NAND gate
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