Lab 7

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Michigan State University *

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410

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Electrical Engineering

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Dec 6, 2023

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Lab 7: 8-bit Shift Register Design and Power Measurement Due by Friday April 2 Summary: In this group lab, an 8-bit Shift Register will be designed as the last component of your custom cell library. Design techniques for higher level digital functional blocks using custom IC design tools are practiced and power analysis of a custom IC is introduced. Learning Objectives: 1. Observe the functionality of a digital shift register circuit. 2. Learn how to measure power consumption of an IC 3. Learn how to design schematics and layouts for multi-input/output bit structures. Important Notes:  This is a group lab , to be completed by 3-person groups. Team organization and distribution of workload will be determined by individual groups. This lab is more complex than the prior individual labs, so plan well, divide and conquer.  Each group will submit a single report. All group members should be present at the time of check-off and should understand all the elements of the lab.  As with every layout you construct, you must try to minimize the layout area and keep the cells as compact as possible. Resources: Besides the documents you have used so far, the following document is useful for completing this lab and is available on the class website.  Guide to Power Measurement Procedure: 1. Using DFFR and multiplexer cells that you designed in previous lab, construct an 8-bit shift register that can implement the truth table given here. Refer to class notes and the appendix at the end of this lab instruction. a. Complete the schematic and verify proper functional operation using schematic-level simulations. You do not need to include these in your report, but you should not begin the next step until you know ALL FUNCTIONS of the shift register are working correctly. Use a clock of 50MHz. b. Construct the layout of the 8-bit shift register placing all cells in a single row with the same power supply rails. Pass DRC and LVS. Before extracting, remember to run the Truth Table for Shift Register S2 S1 S0 Function 0 0 X Parallel Load 0 1 0 Shift Right 0 1 1 Rotate Right 1 0 0 Shift Left 1 0 1 Rotate Left 1 1 X Set ( data output bits go to 1) X X X Reset (when Reset = 1, all data outputs go to 0)

command NCSU_parasiticCapIgnoreThreshold=1e-18 in the Command Interpreter Window to include the parasitic capacitances in the extracted view. c. Complete post-layout simulation for the shift register with CLK at 50MHz. Simulate all functions in the truth table and determine the slowest function. Do a final simulation of this function to show in your report. Perform a parallel reset of all 8 bits at the beginning of your simulation and measure the worst-case delays (propagation & rise/fall times) for the slowest function of the cell. If necessary, refer back to Tutorial C for post layout simulation guidelines. You do not need to report the timing for all functions, just the one with the critical path delay. Read Discussion Topic 1 before continuing. 2. Review the Guide to Power Measurement and measure the following for extracted views of the DFFR cell you designed in the previous lab and the Shift Register: 1) static power dissipation, 2) dynamic power dissipation, 3) total average power dissipation. Note the guide has more information than you need to complete this step; the other material is just for your reference. For the DFFR cell, use a simulation with a 50MHz clock and toggle the D input high and low for two cycles at 20MHz (i.e., run simulation for 100n). For the Shift Register cell, use your worst-case delay simulation. To avoid unpredictable start-up states, toggle the reset line at the beginning of your simulations (initiate reset to low and immediately pull it high). 3. {Do this step for 10% Extra Credit only; it is not required} Using the DFFR cell, construct the schematic for an asynchronous counter that can count to eight (0-7). Perform a schematic- level simulation that verifies counting over 10 input cycles. Include the plot in your report and use hand or typewritten annotations to clarify proper operation. 4. See the table below to find out what the deliverables are. Include this table in the first page of your report and make sure your report has all the required deliverables specified by “x” in the “report” column. Include responses to the Discussion Topics below in your report. Deliverables: check off lab report 1 Schematic and layout of the 8-bit Shift Register X X 2 LVS results for 8-bit Shift Register X 3 Post-layout simulation graphs and specified results for Shift Register X 4 Power measurements of DFFR and Shift Register X 5 {5% Extra Credit} Schematic of 0-7 asynchronous counter X X 6 {5% Extra Credit} Simulation results for 0-7 asynchronous counter X Discussion Topics Include type-written responses to the following discussion topics in your brief report. 1. Briefly discuss the worst-case function of the shift register. Is it what you expected? Why or why not? 2. Briefly discuss the pros and cons of the asynchronous counter verses a synchronous counter. Answer this question even if you did not complete the extra credit step.

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