Lab 6 Report

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School

Pennsylvania State University *

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Course

310

Subject

Electrical Engineering

Date

Dec 6, 2023

Type

docx

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8

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Moses Tonade Lab 6 Report Introduction In this lab we will be using an nMOS transistor as our active load working in parallel with two pMOS transistors acting as a current mirror. Circuit Schematics Task 1 In this figure, the current mirror schematic is shown where Q3 and Q2 are pMOS transistors and carry the current from the active load. The drain to gate voltage in this figure on Q3 - 0V, we assume that the device is operating in the saturation region.
Moses Tonade Lab 6 Report Task 2 Within this figure, we added a Q1 nMOS transistor, which is a common source amplifier. Resistors 1 and 2 had to be selected in order to allow the transistors to work in the saturation region still. Task 5 This common gate amplifier was created by removing the AC signal from the negative side of the capacitor.
Moses Tonade Lab 6 Report Task 7 For this task we needed to remake the circuit to where the output voltage was proportional to the nMOS transistor’s transconductance parameter. From this we made a small signal circuit to figure out the theoretical gain. Data and Graphs Task 1 I DS = 1 2 k p ( V SG 3 | V Tp | ) 2 Using this equation where I DS = 100μA, k p = 850μA/V 2 , and V Tp = 1.55. We can find V SG3 to be equal to 2.03 V. Also using V S = 10V, V SG = 1.45V, we find V G = 7.49V. Using V/I, we can find R 3 by dividing 8.21V by 100μA leaving R 3 = 74.9 kΩ Task 2 I REF = 1 2 k n ( V GS 1 V tn ) 2
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