Architecture HW8

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Auburn University *

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7300

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Electrical Engineering

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Dec 6, 2023

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docx

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4

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1. What are the differences between Programmed I/O, Interrupt-Driven I/O and DMA? Programmed – CPU is designated the task of transferring data from memory. While cheap and simple, it can be highly inefficient due to the need of the CPU to work with every data transfer through the starting, waiting for completing process. Good for low demand traffic. Interrupt-Drive – Here the CPU starts the I/O process but moves on without waiting allowing it to continue executing the other tasks waiting to be completed. When the process finishes, an interruption is created to tell the CPU it has finished. This allows the ISR to take over and complete the I/O operation process. This leads to a more efficient method as it allows the CPU to do other tasks while these processes occur. Good for day to day usage. DMA – Direct Memory Access uses a DMA controller to manage the process of data transfer without the need of the CPU. The CPU gives the controller the necessary information and then hands over the processes to this controller. Due to this, it is good for high demand traffic because it allows for almost complete CPU removal from the process. 2. Discuss the different ways of mapping I/O addresses to the processor address space. There were two main ways discussed in class and they are as follows: Memory Mapped: This allows for I/O devices to be stored in the normal memory address space while assigning specific addresses to I/O devices allowing for all the information to be found in a known specific location. Isolated: This picks a designated address space to designate to I/O operations. This means the CPU has completely different instructions/address lines for I/O operations than memory operations meaning that the two can be clearly seen as separate. Is extremely simple and found in older computers.
3. A DMA module is transferring characters to memory using cycle stealing, from a device transmitting at 18,300 bps. The processor is fetching instructions at the rate of 4 million instructions per second (MIPS). By how much will the processor be slowed down due to the DMA activity? 1 char is transferred per trip on bus Transfer rate = 18,300/8 = 2287.5 chars/sec Instruction fetch rate = 4 million instructions/sec Slow down = (2287.5/4 million) x 100% = .00057188 x 100% The above does not represent complete total slow down, as the processor can do some other things but is good for general equation.
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