Lab 7

New Solution

Question 1: Use Indirect addressing to write a PIC24 assembly code that complements and adds 5 and multiply by 2 to 1024 data bytes into the memory at starting address Ox1000. The original data are stored in the memory starting from address 0x800. it is an electrical engineering question . this is the full information about the question!

the diagram on the right is for a register bank circuit that contain 8 registers. Each register is 16-bit. The register can read or write to one register at a time using address bus. Design the circuit and specify the width of EVERY bus.

c) Given a 32K x 8 RAM chips. Compute: i) the number of chips needed to build a 128K byte memory using 32K x 8 RAM. ii) the number of address lines that must be used to access the memory. iii) the number of lines connected to the address inputs of each chip, the number of lines to be used for chip select inputs and type of decoder to be used. iv) Determine the range of addresses for the 128K byte memory.

Q. To interface memory with the microprocessor, connect register the lines of the address bus must be added to address lines of the chip. A. single B. memory C. multiple D. triple

What is the maximum memory size that can be connected to a processor with a lower order address bus of 24 lines and a higher order address bus of 4 lines? a. 256GB b. 16MB c. 256MB d. 16GB

Assume that memory location $c100 holds a data byte =$37, [ACCA]= $B8 and [ACCB]=$FE. For each of the following instructions determine the resultant content of ACCA or ACCB. (a) ANDA $C100 (b) ANDA #$05 ORAB #$EE (c) (d) CLR B (e) NEGA (f) DECB (g) ASLA (h) LSRB (i) EORA #$E4 (G) ROR A

3- what is the advantages of memory segment. 4- state the purposes of segment registér. 5- what is the different between general purpose register and segment register and flag register.

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part d, e, f

- The stack memory is addressed by a combination of the plus offset. The PUSH and POP instructions always transfer between segment -bit number the stack and a register or memory location in the 8086 microprocessors. For string instructions, DI always addresses data in the segment. The 8086 LOOP instruction decrements register for a 0 to decide if a jump occurs and tests it

8085 Microprocessor

Q3/(A) False OR True 1- A0-0 and BHE-1 are used as low bank-select signal: 2-AX is 2234 H after executing the following instruction: AAS. If AX-2234H. 3-IP register holds the offset address of the next instruction to be executed. 4- The XLAT instruction in 8086 assembly language is used to perform arithmetic operations between two memory operands. 5- Bus interface unit is responsible form

computer architecture and organization

Describe any possible methods through which you can implement a RAM memory using logic gates?

Memory interfaced to 8086 Microprocessor 16 data bus should be arranged in-------- a.One bank. b.Two bank c.Three bank. d.Four bank JC mean jump to specific address when the CF in the flag bit is = a. zero b.two c.one d.three Overflow flag bit indicates overflow for a.Signed integer only. c. Signed and Unsigned integer only. The 8086 architecture consists pipeline processing. b. Two b. Three arithmetic operations. b. Unsigned integer only. d. Floating point. unit(s) work in parallel is called c.Four d.One

3. Suppose r0=0x20000000 and r1=0x12345678. All bytes in memory are initialized to 0x00. Suppose the following assembly program has run successfully (the three instructions will be executed in the given order). Draw a table to show the memory value if the processor uses little endian. STR r1, [r0], #4 STR r1, [r0,#4]! STR r1, [r0, # 4] Address 0x20000010 0x2000000f 0x2000000e 0x2000000d 0x2000000c 0x2000000b 0x2000000a 0x20000009 0x20000008 0x20000007 0x20000006 0x20000005 0x20000004 0x20000003 0x20000002 0x20000001 0x20000000 Data

THE FOLLOWING QUESTION CONTAINS ALL THE REQUIREMENTS NEEDED.

b) The number of addressed words in a ROM is determined from some fact. 92 X 8 ROM architecture support those facts? Whát will be the capacity?

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Consider the following assembly program MOV CX, 1100H DLY: SUBS CX, CX, #1 NOP BNE DLY NXT: --- (a) How many times does the BNE DLY instruction get executed? (b) Change the first line of the program so that BNE DLY is executed 34 times (c) Change the second line of the program so that BNE DLY is executed 34 times, while the fist line stays unchanged (MOV CX, 1100H)

6- Set BX to 4567H, CX to FEDCH and SP to A59FH, then run the instructions: PUSH BX PUSH CX a. What is the new value of SP ? b. Display the memory locations where you pushed the values of BX and CX in the stack.

What is the maximum memory size that can be connected to a processor with a lower order address bus of 24 lines and a higher order address bus of 4 lines? a. 256GB b. 16MB c. 256MB d. 16GB Note: Please do not handwritten.

An 8051 subroutine is shown below: SUB: RO, #20H @RO , #0 MOV LOOP: MOV INC RO CJNE RO, #80H, LOOP RET a. What does this subroutine do? b. In how many machine cycles does each instruction execute? How many bytes long is each instruction? C. d. Convert the subroutine to machine language. e. How long does this' subroutine take to execute? (Assume 12 M

Consider the following external memory connections to a microcontroller which is similar to that of a microprocessor. What is the size of the memory? Microcontroller RAM/ROM 3 O A. none of the choices O B. Could be 4 x 3 bits or 16 x 3 bits O C. Could be 4 x 16 bits or 4 x 3 bits O D. 4 x 2 bits O E. 8x3 bits 2

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