ECE645 HW1 Spring2023

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Kansas State University *

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Course

645

Subject

Electrical Engineering

Date

Apr 3, 2024

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pdf

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1

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ECE 645 Digital Electronics Spring 2023 Homework #1 1) (35 pts) Using PSpice, recreate the initial simulation from Design Metrics-Part1 in the ECE645 Resource Manual. Use the baseline size transistors and verify that you get the same values for threshold voltage ( V t ), threshold voltage gain ( A v ), NM H and NM L that is found in the initial simulation found in the Resource Manual. This will let you know if you have your modified transistors working properly and that your circuit constructed properly. Documentation to turn in: a) Schematic Diagram b) Plot of Output vs Input for the inverter c) Either Graphical work showing how you found the unity gain points, Vt, and threshold gain, or a plot of the derivative of the output curve with these point marked d) Calculations of NM L and NM H 2) (45 pts) Using PSpice again, simulate a modified version of the inverter, with the sizes of the FETs altered. Set M=120 for the p-channel device and M=10 for the n-channel device . Again, find the Threshold Voltage ( V t ), the threshold voltage gain ( A v ), NM H , and NM L ). Compare these values to what you found in part 1). Documentation to turn in: a) Schematic Diagram b) Plot of Output vs Input for the inverter c) Either Graphical work showing how you found the unity gain points, V t , and threshold gain, or a plot of the derivative of the output curve with these point marked d) Calculations of NM H and NM L e) Comparison of the V t , A v , NM H , and NM L for the two inverters f) Copy an Output file which contains all the computer code including the net list for the circuit, the analysis used on the circuit and the MOSFET models from the tech files
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