WA Unit 2 (Comms & Networking)

Solve it fast plz

all steps with exmaples and theory please

The implementation of a 4-1 multiplexer NOTfollowing the hierarchical design technique andusing gates with fan in and fan out = 4, …Requires 4 AND gates & 1 OR gate, on 2 levels ARequires 8 AND gates & 2 OR gates, on 3 levels BRequires 2 AND gates & 1 OR gate, on 2 levels CRequires 4 AND gates & 1 OR gate, on 3 levels DNone of previous answers E   apparently answer is A so  solve this question in great detail explaining every single bit of info as i'm a complete beginner and i need to understand how to solve questions of this type. also provide small examples of how the solution would differ if the question was slightly altered

the following blanks with a word or phrase: wires in a measurement circuit and a nearby mains-carrying conductor. w interferenc us source also known as electrostatic coupling, can occur between the signal s and wires in a measurement circuit and a nearby mains-carrying conductor. rom 2A type of optical sensors that can detect the presence of objects within its vicinity without any actual physical contact is called 3. A Sensa-is a device that measures a physical quantity and converts it into a signal which can be read by an observer er by an instrument. 4. The photons hitting the photovoltaic cell pass through the and are absorbed by electrons in the Hin p-doped upper layer S. The ability of an op amp to suppress common-mode signals is expressed in terms of its 6. The --- noise arises from fluctuations in the number of charge carriers. 7. The information in much the same way as the mind. - instrument are computing, manipulating, and processing 8. In variable capacitance transducer used…

(b) Figure Q.4b shows an Adder/Subtractor circuit implemented using Adder Q. The delay for XOR = 2t, OR = AND=1t and cascadable full adder is used for ripple carry adder. Assume inputs X, Y and ADDSUB have arrived at Ot. Analyze the critical path delay for the circuit if:- X[7.4] YI7.4] 4. A[3.0] A[3.0] lo"cle C4 C8 C4 Adder Q co C4 Adder Q co ADDSUB Sum(3.0] Sum[3.0] Z17.4] Figure Q.4b i. Adder Q is a 4-bit Ripple-Carry Adder. Show your analysis in Table Q.4b.i. ii. Adder Q is a 4-bit Carry-Lookahead Adder. Show your analysis in Table Q.4b.ii. Table Q.4b.i Table Q.4b.ii To Node Delay To Node Delay Z3 Z3 С4 С4 Z7 Z7 C8 C8 Page 14 of 21

In a communication system the signal sent from point a to point b arrives by two paths in parallel. For path 1, the signal passes through two repeaters ( in series ). Each repeater has probability of failing ( becoming an open circuit ) of 0.1. For path 2, the signal passes through one repeater with a probability of failing of 0.08. All repeaters fail independently of each other. Find the probability that the signal will not arrive at point b. O 0.0152 O 0.016 0.008 0.09

Complete 4

To implement 8-to-1 line multiplexer using two 4-to-1 line multiplexer(MUX): O a. The third selctor is connected to the enable line of the first and second MUX. O b. Only the enable line of the first MUX must be connected dirictly to the enable for the second MUX. O c. The third selctor is connected to the enable line of the first MUX which is connected through inverter to the enable of the second MUX. O d. All inputs lines for the first mux must be connected to the input lines for the second mux.

For the signal flow graph of the given figure consider the following statements: 1. It has three forward paths. 2. It has three individual loops. 3.lt has two non touching loops. out of above the correct statements are X2 X3 X6 X1 1,3 O 2, 3 1, 2, 3 O 1,2

The Vrms value is wrong

4-a) what are the application of gray code? b) what is the advantages of the gray code?

Choose the correct Answer: The difference in the propagation delay between the fastest and slowest pairs of the same un-twisted pair cable is called, O a. Delay Distortion O b. Propagation Speed O . Propagation Time O d. Delay Skew O e. Cross Talk