EECS_140_Lab 7_four_bit_adder

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School

University of Kansas *

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140

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Electrical Engineering

Date

Jan 9, 2024

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pdf

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Uploaded by ColonelElectronDolphin32

Lab 7: EECS 140 Four Bit Adder1 Adder with Display Objectives The objective of this laboratory exercise is for you to learn how to use modular design in VHDL to create a real world application by implementing an adder unit into an FPGA chip and display the addition result. You will use Xilinx Vivado software to implement a 4-bit adder circuit. You will then connect the result of the adder to the input of your display drivers (from the previous lab). Finally, you will download the circuit design to the board and will test proper functionality of the circuit. An eight bit slide switch will be used for implementing two 4-bit numbers as inputs, the addition will be outputted on two seven segment displays. Discussion

Click here to view the 4-bit full adder block diagram(better quality) Figure 1: Flow chart for Four bit adder (140 students)

We will also introduce modular design for VHDL . This is a powerful tool to streamline FPGA design, avoid code repetition and enhance portability, re-usability and abstraction. For this lab, you will need to write VHDL modules for three components and then instantiate them in the toplevel.vhd file. Look at examples in the modular VHDL tutorial attached above for syntax and usage. • 1 bit full adder: You will have to edit the bit_full_adder.vhd file to include the expressions for sum and carry out of the 1 bit full adder. • display_driver: You have already done this is the last lab. This component takes in a 4-bit input and outputs 7 bits controlling the 7 segments. • LEDdisplay: This component is used to switch between the outputs of display_driver1 and display_driver2 (refer the block diagram attached above). Your outputs on the 2 seven segments will range from 00 to 1E (00 to E1 for multiplier). Tasks VHDL files Figure 2: Flow chart for Four bit multiplier(141 students)

Download and Add these source files to your new project project navigator. (Right click->Save link as). Also change the file extension to .vhd. EECS 140 students download file 1-4, 141 students download 1-3 and 5-7. 1. bit_full_adder.vhd 2. display_driver.vhd 3. LEDdisplay.vhd 4. toplevel.vhd 5. multiplier flow chart (Honors) better quality 6. bit_mult.vhd (Honors) 7. toplevel.vhd (Honors) Pre Lab Please answer the following questions and submit to your TA at the start of the lab: 1. (Previous Lab) Why did we have to negate the outputs of the seven segment display? 2. If we wanted the display to light up the left seven segment LEDs instead of the right ones, what would we change? 3. (Current Lab) What's the basic component we will use to implement our 4-bit adder? 4. What kind of 4-bit adder are we designing? 5. What is the significance of the "Anodes" (AN0, AN1, AN2, and AN3) ? Step 1: VHDL Tutorials If you haven't done so yet, review the following tutorials for VHDL and mudular VHDL. Pay special attention the the modular VHDL tutorial, as from now on we will use modular VHDL almost exclusively. • This VHDL tutorial will teach about the VHDL language, its fundamentals, and how to represent a simple circuit in VHDL. • This Modular VHDL tutorial will teach about the using components in VHDL, and creating larger entities by structural design. Step 2: Ripple Carry Adder Design (bit_full_adder.vhd) You should have a good idea of the adder design concept as well as some basic VHDL. The main idea behind thisapproach is to start little, then build big. Hence: * Use the classic truth table, Kmap, Sum-Of-Products approach to get the equations for your outputs (S and Cout). * Edit the bit_full_adder.vhd file with the equations for sum and carry out, that is architecture (Similar to Lab1,2,3).

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