10. Consider the following VHDL code. ENTITY simple IS PORT( a, b, c: IN std logic; x: OUT std logic); END simple; ARCHITECTURE arc OF simple IS BEGIN x<= (a OR (b AND NOT c)): END arc; a. How many inputs are there and what type? b. How many outputs are there and what type? c. Draw the logic circuit schematic that is equivalent to the VHDL code.

do 3 and 4 and show circuit diagram

Draw the logic diagram (synthesis output) using D F/F for the following HDL descriptions a evaluate the output values of b and c variables. (a) module blocking (clk,a,c); (b) module nonblocking (clk, a, c); input clk; input clk; input a; output c; input a; output c; wire clk: wire a: reg c; reg b; always @ (posedge clk ) begin b = a; c = b; end endmodule wire clk; wire a: reg c; reg b; always @ (posedge clk ) begin b <= a; c<= b; end endmodule

I really need help answering these questions pls  1. A variable is a symbol in Boolean algebra used to represent(a) data (b) a condition(c) an action (d) answers (a), (b), and (c) 2. The Boolean expression A + B + C is(a) a sum term (b) a literal term(c) an inverse term (d) a product term 3. The Boolean expression ABCD is(a) a sum term (b) a literal term(c) an inverse term (d) a product term 4. The domain of the expression ABCD + AB + CD + B is(a) A and D (b) B only(c) A, B, C, and D (d) none of these 5. According to the associative law of addition,(a) A + B = B + A (b) A = A + A(c) (A + B) + C = A + (B + C ) (d) A + 0 = A 6. According to commutative law of multiplication,(a) AB = BA (b) A = AA(c) (AB)C = A(BC ) (d) A0 = A 7. According to the distributive law,(a) A(B + C) = AB + AC (b) A(BC) = ABC(c) A(A + 1) = A (d) A + AB = A 8. Which one of the following is not a valid rule of Boolean algebra?(a) A + 1 = 1 (b) A = A(c) AA = A (d) A + 0 = A 9. Which of the following rules states that…