For the given VHDL program, rectify the logical and syntax errors. Highlight each error and write the corrected codes for each with justification. library ieee; use ieee. std_logic_1164; entity sample is port(a,b: in std_logic; X: out std_logic; Y: out std_logic vector(2 down to o)); end sample; architecture sample 1 of sample is begin signal R: bit:=’U’; if a=’1’ then Y<=”00”; R<=’1’; elsif b=’1’ then Y<=”01”; R<=’0’ else Y<=”11’;R<=’0’; end process; X<=R;end sample1;

Write the AHDL code to implement acomparator such that the output z is LOW only whenthe input digital_value is between 6 and 11(inclusive).

Create a Test Bench file for the following VHDL code: library IEEE;use IEEE.STD_LOGIC_1164.ALL; entity shiftregister is    Port ( R : in  STD_LOGIC_VECTOR(5 downto 0);           L, w, Reset : in  STD_LOGIC;           Q : out  STD_LOGIC_VECTOR(5 downto 0));end shiftregister; architecture Behavior of shiftregister issignal Sreg : STD_LOGIC_VECTOR(5 downto 0);beginif reset='1' thenSreg <= "000000";elsif clk'event and clk='1' thenif L='1' thenSreg <= R;elseSreg(0) <= Sreg(1);Sreg(1) <= Sreg(2);Sreg(2) <= Sreg(3);Sreg(3) <= Sreg(4);Sreg(4) <= Sreg(5);Sreg(5) <= w;end if;end if;Q <= Sreg;end process;end Behavior;

Write a SystemVerilog module for the following function, as defined by the truth table. Use assign statements, and express the equation in minimized sum-of-products (SOP) form. The module declaration for part (a) is below. Fill in the body of the module. Name the other modules: ex1b and ex1c. module ex1a(input logic a, b, c,                    output logic y); // Fill in the body of the module. endmodule