A compiler designer is trying to decide between two code sequences for a particular computer. The hardware designers have supplied the following facts: CPI for R-type instruction is 1, CPI for l-type instruction is 2, and CPI for J-type instruction is 3. The two sequences have the following instruction counts: Code sequence 1: R-type (2), l-type (1), J-type (2) Code sequence 2: R-type (4), l-type (1), J-type (1) How many clock cycles are required for code sequence 2?
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- A compiler designer is trying to decide between two code sequences for a particular machine. The hardware designers have supplied the following facts: Instruction class CPI of the instruction class A 1 B 3 C 4 For a particular high-level language, the compiler writer is considering two sequences that require the following instruction counts: Code sequence Instruction counts (in millions) A B C 1 2 1 2 2 4 3 1 a. What is the CPI for each code sequence? b. Which code sequence is faster? By how much?Compare compilers A and B for a program, where compiler A results in a dynamic instruction count of 6.9x10^9 and an execution time of 5 seconds, and compiler B results in a dynamic instruction count of 5.1x10^9 and an execution time of 4 seconds. a. Find the average CPI for each program, given a processor clock cycle time of 2 ns. b. If the compiled programs run on two different processors with the same execution times, what is the relative speed of the processor clocks?1. fast please in assembly language You are giving the before condition and an instruction. Give the after condition: Before: Eax: 00 00 00 0A Ebx: FF FF FF FB Edx: FF 03 FF 01 Instruction Executed: imul bx Group of answer choices 1.eax: 00 00 FF CE edx: FF 03 FF 01 2.eax: 00 00 FF CE edx: FF 03 FF FF 3.eax: 00 00 00 CE edx: 00 00 00 00 4.eax: FF FF FF CE edx: FF FF FF FF
- Microprocessor lab tasks - Solve the problems in assembly language using emu8086 solution format .MODEL SMALL .STACK 100H .DATA ; DEFINE YOUR VARIABLES HERE .CODE MAIN PROC MOV AX, @DATA MOV DS, AX ; YOUR CODE STARTS HERE ; YOUR CODE ENDS HERE MOV AX, 4C00H INT 21H MAIN ENDP END MAIN Collapse :white_tick: 1 Problems : Task 01 a program that takes in 3 digits as input from the user and finds the maximum Sample input: 1st input: 1 2nd input: 2 3rd input: 3 Sample Output: 3 Task 02 Take two digits as input from the user and multiply them. If the result is divisible by 2 and 3 both, print "Divisible". Otherwise, print "Not divisible" Sample input: 1st input: 5 2nd input: 6 Result is 30 Sample Output: Divisible Sample input: 1st input: 5 2nd input: 2 Result is 10 Sample Output: Not divisibleSuppose the implementation of an instruction set architecture uses three classes of instructions, which are called A, B, and C. The total dynamic instruction count is 1 x 10^7 and the processor's clock rate is 2.5 GHz. Details for the three classes are given in the table below: Class CPI % of instructions A 1 20% 50% C 3 30% Complete the following table. Express all answers in scientific notation and round to two decimal places, when needed. Class Instruction Count Number of Clock Cycles х 10^ x 10^ A х 10^ х 10^ x 10^ х 10^ CThe three alternative designs for a computer's central processing unit (CPU) are a general register, a single accumulator, or a stack. Each one has a unique set of benefits and drawbacks. It is up to you to respond, and the response you give might be right or it might be wrong.
- The purpose of this project is to gain a greater understanding of the Intel 32-bit instruction set and understand how a compiler translates C code into assembly language. By compiling the program in unoptimized mode you will hopefully see a fairly clear translation. When running in optimization mode, you will see how well compilers can optimize your code. To compile an unoptimized version use: gcc -Wa,-adhln -g -masm=intel -m32 "Project 2.c" > "Project 2.asm" To compile an optimized version use: gcc -Wa,-adhln -O -masm=intel -m32 "Project 2.c" > "Project 2-o.asm" The -Wa,-adhln option causes gcc to generate intermixed source and assembly code. The -masm=intel option causes gcc to generate assembly code in intel format. The -m32 generates 32-bit code. The -g option generates unoptimized code while -O generates optimized code. The generated code includes quite a few directives that can be ignored. Most of the directives begin with a period (.). There are also a few call…Using C programming language write a program that simulates a variant of the Tiny MachineArchitecture. In this implementation memory (RAM) is split into Instruction Memory (IM) and DataMemory (DM). Your code must implement the basic instruction set architecture (ISA) of the TinyMachine Architecture:1 -> LOAD2 -> ADD3 -> STORE4 -> SUB5 -> IN6 -> OUT7 -> END8 -> JMP9 -> SKIPZEach piece of the architecture must be accurately represented in your code (Instruction Register, ProgramCounter, Memory Address Registers, Instruction Memory, Data Memory, Memory Data Registers, andAccumulator). Data Memory will be represented by an integer array. Your Program Counter will beginpointing to the first instruction of the program. Input SpecificationsYour simulator must run from the command line with a single input file as a parameter to main. This filewill contain a sequence of instructions for your simulator to store in “Instruction Memory” and then runvia the…Write down the machine code of the following assembly instructions for 8088/8086 processor inthe space on the right of each instruction. You can use the handout given to you for assembling theinstructions. AnswerMOV DS, AX; 8ED8XOR DI, DI;MOV DI, 1600;MOV CX, 256;SUB AL, AL;
- As a result, the specific mechanisms by which an instruction obtains its input data are decoupled from the specific means by which any other instruction obtains its input data. Use with a(n): A Synthesizing data sets using procedural descriptions B In contrast to the case of "multiple data, multiple instruction," in which C D stands for "data alone," there is just a single instruction. Many outcomes from a single orderThe CPU design team is designing an instruction set with three classes of instructions. Parameters are given in the following table. Consider a program with 65% ALU instructions, 25% memory access instructions, and 10% control instructions. What is the average CPI for this CPU? Clock Rate 4GHz CPI for ALU Inst. 6 CPI for Memory Inst. 8 CPI for Control Inst. 2Convert the given code fragment to assembly code fragment, using only instructions of the following types. These instructions are generally discussed in class. Here X,Y,Z are any memory locations; R, R1, R2 are any general registers; L is a label in the code (you can use any names as labels, ex. L, L1, L2 etc. ). load X, R //copy contents of memory location X into R. store R, X //Store contents of R into Mem location X cmp R1, R2 //Compute R1-R2 and update condition codes; //throw away result of subtraction. jmp L //Jump to location L in the code. jmpp L //If P bit is 1, Jump to location L in the code add X, R //Add contents of X,R and store result in R; //Also update the condition codes. Be careful about what type of argument is allowed in the instruction (Memory or Register). Ex. the first argument of ADD instruction is memory, not register. Do Not…