1. Consider the following program in MARIE assembly language. a) Complete the table detailingthe RTN for next 2 instructions only that will be executed including the content of registers PC,IR, MAR, MBR and AC in hexadecimal. Note the first instruction LOAD X is already filled. Notealso that SKIPCOND instruction has no operands, therefore you can complete Fetch, decode andexecute cycles only. b) Explain in one statement the task performed by this program?LOAD X/ AC = Xif AC > 0 then PC = PC + 1 (skip)/ Go to EndRepeat, SKIPCOND 800JUMP EndSUBT One/ AC = AC - 1STORE X= ACJUMP RepeatGo to RepeatSTORE XEnd, HALT/ Stop (end of program)х,DEC 10One,DEC 1labelopcodeLOADoperandhex0000OUTPUTAC0001007001RepeatSKIPCOND 80e880e0022JUMPEnd9a06IR0000003SUBTOne4008O 004JUMPRepeat9001MAR000005STORE2007O 006EndHALT7000MBR 0000007DEC10O 008ОneDEC0001PC000INPControl+0 +1 +2 +3000 1007 BBee 9006 4008 9881 2007 7000 a00A 88a1 eeee eee e000 eeea eeee eeee e000010 eeea eeee o00e a000 eeaa eeee e00 aa00 8aaa peee oee ea00 eeea eeee oe0e eeee+4+5 -6+7+8 +9+A+C+D+E+F020 eeee eeee eeee a000 eeaa eeee e000a000 eaaa eeee ee00e000 eeaa eeee eeee eeee030 eeee eeee o00e e000 eeaaeeee 0000 a000 88a eeee o000 e000 eee0 eeee 00 0000eeaa eeee eeee aeeeee00 eeee eeee ae000000 e000 eaaa eeee eeee ee00 eeea eeee 00ee e00e040 e0ee eeee eeee ae0e eeaaeeee e00e aa0e eaaa eeee eeee ee00050 eeee eeee oeee a000 eeaaeeee 0000 a000 8888 eeee oeee 0000060 eeee eeee eeee eee eeee eeee070 eeee eeee eeee a000 eeea eeee e00e e000 eaaa eeee ee00 e000 eee0 eeee e0ee e0ee080 ee0e eeee 000e 0000 eeaa eeee e00e ag00 e8aa eeee ee00 e000 ee00 eeee o000 0000InstructionStepRTNPCIRMARMBRACMAR O PC000 | 000000000000000FetchIR O M[MAR]000 100700000000000РС О РC + 1001 | 100700000000000Decode OPCODEIR[15-12]=0001001 | 100700000000000Load XDecode=> LoadMAR O IRL11-0]001 | 100700700000000GetMBR O M[MAR]0011007007000A0000operandexecuteАС О МAR0011007007000A000A

Consider the following program in MA dE assembly language. a) Complete the table detailing the RTN for next 2 instructions only that will be executed including the content of registers PC, IR, MAR, MBR and AC in hexadecimal. Note the first instruction LOAD X is already filled. Note also that SKIPCOND instruction has no operands, therefore you can complete Fetch, decode and execute cycles only. b) Explain in one statement the task performed by this program? / AC = X if AC > 0 then PC = PC + 1 (skip) LOAD X Repeat, SKIPCOND 800 / Go to End / AC JUMP End SUBT One AC

Consider the following program in MA dE assembly language. a) Complete the table detailing the RTN for next 2 instructions only that will be executed including the content of registers PC, IR, MAR, MBR and AC in hexadecimal. Note the first instruction LOAD X is already filled. Note also that SKIPCOND instruction has no operands, therefore you can complete Fetch, decode and execute cycles only. b) Explain in one statement the task performed by this program? / AC = X if AC > 0 then PC = PC + 1 (skip) LOAD X Repeat, SKIPCOND 800 / Go to End / AC JUMP End SUBT One AC

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Consider the following program in MARIE assembly language. a) Complete the table detailingthe RTN for next 2 instructions only that will be executed including the content of registers PC,IR, MAR, MBR and AC in hexadecimal. Note the first instruction LOAD X is already filled. Notealso that SKIPCOND instruction has no operands, therefore you can complete Fetch, decode andexecute cycles only. b) Explain in one statement the task performed by this program?
Consider the following program in MARIE assembly language. a) Complete the table detailing the RTN for next 2 instructions only that will be executed including the content of registers PC, IR, MAR, MBR and AC in hexadecimal. Note the first instruction LOAD X is already filled. Note also that SKIPCOND instruction has no operands, therefore you can complete Fetch, decode and execute cycles only. b) Explain in one statement the task performed by this program?
Consider the following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers (see image 1). Assume the use of a four-stage pipeline: fetch, decode/issue, execute, write back. Assume that all pipeline stages take one clock cycle except for the execute stage. For simple integer arithmetic and logical instructions, the execute stage takes one cycle, but for a LOAD from memory, five cycles are consumed in the execute stage. If we have a simple scalar pipeline but allow out-of-order execution, we can construct the following table for the execution of the first seven instructions (see image 2). The entries under the four pipeline stages indicate the clock cycle at which each instruction begins each phase. In this program, the second ADD instruction (instruction 3) depends on the LOAD instruction (instruction 1) for one of its operands, r6. Because the LOAD instruction takes five clock cycles, and…
6. Assume that two numbers: dividend and divisor are saved in memory address M1 and M2 respectively. Quotient and remainder should be saved in R1 and R2 respectively. Write assembly language instructions and then list microoperations for each instruction and list the control signals required to be activated for each microoperation. MBR is used as buffer for any register to register transfer operation. Signal Description: Control signals operation Comments C0 MAR to RAM (through address bus) C1 PC to MBR C2 PC to MAR C3 MBR to PC C4 MBR to IR C5 RAM to MBR C6 MBR to ALU C7 Accumulator to ALU C8 IR to MAR C9 ALU to Accumulator C10 MBR to Accumulator C11 Accumulator to MBR C12 MBR to RAM (through data bus) C13 IR to Control Unit C14 MBR to R1 C15 MBR to R2 C16 MBR to R3 C17 MBR to R4…
For the MIPS assembly instructions below, what is thecorresponding C statement? Assume that the variables f, g, h, i, and j areassigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume thatthe base address of the arrays A and B are in registers $s6 and $s7,respectively. Note: for each line of MIPS code below, write the respective Ccode. After that, write the corresponding C code for the MIPS.sll $t0, $s0, 2add $t0, $s6sll $t1, $s1, 2 add $t1, $s7, $t1lw $s0, 0($t0)addi $t2, $t0, 4lw $t0, 0($t2)add $t0, $t0, $s0sw $t0, 0($t1)
Q1: Suppose the hypothetical processor has two I/O instructions: (3+3+3)0011=Load AC from I/O0111=Store AC to I/OIn this case, the 12-bit address identifies a particular external device. Show the program execution using figure for the following program:a) Load AC from device 6b) Add contents of memory location 880c) Store AC to device 7 (Note: Question is to be solved similar to the pictures attached with minimum explaination of a line or two with the steps and SHOULD include the memory location 880 as stated in the question)
For the MIPS assembly instructions below, what is the corresponding C statement?Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and$s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. sll $t1, $s1, 2add $t1, $t1, $s6lw $t1, 0($t1)sub $t0, $s3, $s4sll $t0, $t0, 2add $t0, $t0, $s7lw $t0, 0($t0)add $t1, $t1, $t0sll $t0, $s0, 2add $t0, $t0, $s7sw $t1, 0($t0)
Please solve and show all work. Thank you. For the following C statement, write a minimal sequence of MIPS assembly instructions that does the identical operation. Assume $t1 = A, $t2 = B, and $s1 is the base address of C, << is shift left operation. A = C[0] << 12;
Add control states to the following to implement an exchange-with-memory instruction, xchg. such that xchg $rt,immed($rs) acts rather like the combination of a MIPS lw and sw: the result should be as if a sequence like t=memory[immed+rs]; memory[immed+rs]=rt; rt=t; where t is a temporary register. In case you were wondering why one would ever want to do this, it's actually a very common operation for synchronizing between concurrently executing processes using sempahores... but MIPS doesn't happen to do it this way, so it's also not a MIPS instruction. You're probably wondering where the t register is. Well, pick one you're not using... perhaps y (although you have to be careful about when you compute immed+rs for that to work). You should use the encoding suggested by the when below, so an instruction like xchg $9,4($10) would be encoded as op(3)+rt(9)+rs(10)+immed(4). when (op()) (op(3)) XchgStart: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin,…
For the following MIPS assembly instructions what is the corresponding C statement? Assume that variables f,g,h,i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Add comments for each line to describe what each instruction does. addi $t0, $s6, 4 # $t0 = &A+4 = &A[1] add $t1, $s6, $zero # sw $t1, 0($t0) # lw $t0, 0($t0) # add $s0, $t1, $t0 #
More registers appear to be a good thing, in terms of reducing the total number of memory accesses a program might require. Give an arithmetic example to support this statement. First, determine the number of memory accesses necessary using MARIE and the two registers for holding memory data values (AC and MBR). Then perform the same arithmetic computation for a processor that has more than three registers to hold memory data values.
Assume the following register contents: $t0 = 0x01234567, $t1 = 0x56781234. Set back to these values back after answering each question. For the register values shown above, what is the value of registers ($t0, $t1, $t2, $t3) after executing each instruction? sll $t2, $t0, 2 and $t3, $t2, $t1