A processor has the following mix of instruction types, which require different amounts of time to complete the combinational logic for each one. Instruction Time % of Instructions Туре 1 800ps 30% Туре 2 200ps 20% Туре 3 250ps 50% Calculate the total time, the time wasted, and % of the time wasted when executing 10 instructions? 1. -80% 2. -50% 3. -20% 4. -0% A. Total (actual) time: B. Time wasted: C. % Wasted:

A processor has the following mix of instruction types, which require different amounts of time to complete the combinational logic for each one. Instruction Time % of Instructions Туре 1 800ps 30% Туре 2 200ps 20% Туре 3 250ps 50% Calculate the total time, the time wasted, and % of the time wasted when executing 10 instructions? 1. -80% 2. -50% 3. -20% 4. -0% A. Total (actual) time: B. Time wasted: C. % Wasted:

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 15VE: A(n) ________________ instruction always alters the instruction execution sequence. A(n)...

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A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.
How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?
The following table shows the number of instructions for a program with two sequences:Arith Store Load Branch Totala. 650 100 600 50 1400b. 750 250 500 500 2000Assuming that arith instructions take 1 cycle, load and store 5cycles, and branches 2 cycles, and the clock rate is 2 GHz processor.a. Which one is faster?b. Find the CPI for the sequence.b. If the number of load instructions can be reduced by one half,what is the speedup?
Suppose the logic blocks used to implement the processor as discussed in class have the following delays: Instr/Data Memory Access Register File Decode+Read Mux ALU Adder (outside ALU) Single gate delay Register read Register Write Sign Extend 250ps 150ps 25ps 200ps 150ps 5ps 30ps 20ps 50 a) How much time would you expect to take to execute an R-type instruction based on the details studied in class? b) How much time would you expect to take to execute an lw instruction based on the details studied in class? (0.4 c) Based on these two questions, is it possible to guess what would the (minimum) clock cycle time be of such a processor if the instructions are executed in one cycle? If yes, indicate it. If it is not, state the reason why not.
The CPU design team is designing an instruction set with three classes of instructions. Parameters are given in the following table. Consider a program with 65% ALU instructions, 25% memory access instructions, and 10% control instructions. What is the average CPI for this CPU? Clock Rate 4GHz CPI for ALU Inst. 6 CPI for Memory Inst. 8 CPI for Control Inst. 2
8. For a single cycle processor, the instruction breakdown of a program is listed as following. add 20% addi 20% not 0% beq 25% Iw SW 25% 10% What is the percentage of instructions that will use the output of sign extend circuit-module? a. b. What is sign extend circuit-module doing when its output is not needed for current instruction?
In a register/memory type CPU, the instruction lengths are typically variable. This presents a problem when the program is incremented during the Fetch-Decode-Execute cycle. What statements(s) is/are NOT TRUE with regard to Program Counter (PC) incrementing? Select one or more A. The binary loader overcomes the problem by positioning instructions at word boundaries so that PC can be calculated. B . PC is incremented by the largest possible foxed value, irrespective of the variability of the instruction C. Increment value is known when the current instruction has completed execution. D. increment value is known when the current instruction is decoded with the Instruction Register (IR) E. PC incrementing method is implementation dependent
Define pipelining in terms of increasing the speed of a processor, and then determine how many cycles it would take to run five instructions if each part of the machine required the same amount of time. In the absence of pipelining With pipelining, you may do (a), (b), (c), and (d), respectively.
You must show all work for every problem that requires it. The point values for problems may be changed at the professor's discretion. Read each question carefully and follow the instructions. A computer hardware as the following latency for its instructions in Pico seconds: Type Instruction Memory Register Read ALU Operation Data Memory Register Write Total R-Format 250 150 200 0 20 620 lw 250 150 200 250 20 870 sw 250 150 200 250 0 850 beq 250 150 200 0 0 600 J 250 0 0 0 0 250 For a single-cycle implementation what Clock Rate does the machine needs to operate at? For a multi-cycle implementation what Clock Rate does the machine needs to operate at? Provide the type, assembly language instruction and binary representation of instructions described by the following MIPS fields: Op=0x0, rs=3, rt=2, rd=3, shamt=0, funct=34 Op=0x23, rs=3, rt=1, const=0x4 In the snippet of assembly code below, how many times is…
Multiple choice a. Select an instruction form the following that tests bit position 2 of register CH. a. TEST CH, 2 b. BT CH, 2 c. a and b d. NOTCA. After the execution of instruction NEG AX, what will be the value of AX with initialvalue of 01101101? a. 10010010 b. 10010000 c. 10010011 d. 10010100
You are designing a floating point coprocessor which will execute floating point instructions 5 times as fast as the regular processor with zero overhead. Given a workload that contains 25% floating point instructions, what is the speedup achieved by adding the coprocessor to the system? Please give the speedup with exact precision.
Assume that a program requires the execution of 125x106 FP (floating point) instructions, 130x106 INT (integer) instructions, 150x106 L/S (load/store) instructions, and 110x106 branching instructions. These instructions have CPIs of 1, 1, 8 and 4, respectively. Assume that the processor has a 5 GHz clock rate. a. Is it possible to run the program twice as fast if we improve the CPI of just the L/S instructions? If so, by how much? Show your calculations. b. What is the Speedup in the execution time of the entire program if the CPI of INT and FP instructions is reduced by 40% and that of L/S and branching instructions is reduced by 50%?