A program has 75% simple instructions and 25% complex instructions. In RISC, simple instructions take 1 machine cycle and complex instructions are executed as a set of simple instructions, with an average of 12 instructions. Cycle time = 85ns. If a program has 1000000 instructions, then what is the total time taken to execute the program? If, for the same number of simple and complex instructions, CISC architecture is used which takes 4 machine cycles for simple instructions and 9 for complex instructions, what would be the total execution time? The cycle time for CISC is 96ns. Compare these two instruction sets in terms of execution time and state which one is faster.

A program has 75% simple instructions and 25% complex instructions. In RISC, simple instructions take 1 machine cycle and complex instructions are executed as a set of simple instructions, with an average of 12 instructions. Cycle time = 85ns. If a program has 1000000 instructions, then what is the total time taken to execute the program? If, for the same number of simple and complex instructions, CISC architecture is used which takes 4 machine cycles for simple instructions and 9 for complex instructions, what would be the total execution time? The cycle time for CISC is 96ns. Compare these two instruction sets in terms of execution time and state which one is faster.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 3PE: Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one...

See similar textbooks

Similar questions

Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
Suppose you have a computer that does instruction processing in anatomic way, with a clock cycle of 7ns and one instruction executioncompleted every cycle.You now split the processing into the five stages of the RISC pipeline,and you get required processing times of• IF: 1ns• ID: 1.5ns• EX: 1ns• MEM: 2ns• WB: 1.5nsYou now have added 0.1ns of delay between each of these stages. What’s the clock cycle time of this 5-stage pipelined machine?
What would be the clock period of a pipelined MIPS architecture with two stages, one comprising Instruction Fetch, Instruction Decode and Execute, the other one Memory and Write Back? Assume Memory and ALU take 2ns while Registers and other logic take Ins or less.
A RISC instruction pipeline has five stages with propagation delays of 20 ns, 25 ns, 20ns, 70 ns, and 40 ns, respectively. What is the clock period? If a non-pipelined CPU can process an instruction in 160 ns, what is the actual steady-state speedup of the pipeline?
Consider the following sequence of instructions being processed on the pipelined 5-stage RISC processorLoad R4, #100(R2)Add R5, R2, R3Subtract R6, R4, R5And R7, R2, R5 Design RISC Pipelining.
A 512KB memory is to be connected to an 8088 processor using only 64KB memory chips. The starting address is 80000H. What will be the inputs to the NAND gate decoder for the 5th memory chip? Group of answer choices a.) A19=1, A18=1, A17=0, A16=0 b.) A19=1, A18=0, A17=0, A16=0 c.) A19=1, A18=1, A17=1, A16=0 d.) A19=1, A18=0, A17=1, A16=1
What is the clock period of a pipelined MIPS architecture with two stages, one with Instruction Fetch, Decode, and Execute and the other with Memory and Write Back? Assume that memory and ALU take 2ns, and that registers and other logic take Ins or less.
For the following RISC-V assembly instructions below, what is a single corresponding Cstatement? Assume f, g, h, i are in x18, x19, x20 and x21. Your answer must be one single C statementfor all assembly instructions as opposed to one C statement for each assembly instruction. add x18, x19, x20sub x18, x18, x21
Consider a fairly standard 5-stage pipeline: Fetch; Decode; Execute; Memory; Writeback. Let the processor be a nice, simple RISC single-cycle machine. The instructions below are executed. The branch should be taken — however, this processor does no prediction and always assumes a fall-through. Draw a Gantt chart for this and determine the branch penalty. SUB R1, R1, #1 BEQ R1, R0, LoopDone LOAD R2, Memory(100) SUB R3, R2, R1 MUL R3, R3, R3 LOAD R4, Memory(200) ADD R5, R4, R3 STORE R5, Memory(204)
3. If we have an 8 bit microcontroller that has 4kB of instruction memory starting at address 0x0000, and 2kB of data memory immediately above that, what is the next available byte in our address map?
For the following code, determine dependencies and data hazards (along with types). How many clock cycles will be required for RISC V 5-stage pipeline if there is no forwarding hardware? Show with a clock cycle timing diagram. addi x1, x0, 1add x2, x1, x1sub x3, x2, x1slt x4, x1, x2addi x5, x2, -3andi x5, x5, 0x7F0ori x5, x5, 0xFadd x5, x5, x5
On a uniprocessor, portion A of program P consumes 24 seconds, while portion B consumes 822 seconds. On a parallel computer, moderately serial portion A speeds up 4 times, while perfectly parallel portion B speeds up by the number of processors. 1- What is the speedup of program P on 1,024 processors? _______ times 2- How many processors are required to achieve at least half the theoretical maximum possible speedup on P?