Consider the unpipelined machine with10 nano seconds clock cycles. It uses fourcycles for ALU operations and brancheswhereas five cycles for memory operation.Assume that the relative frequencies of theseoperations40%, 20%and 40%arerespectively. Suppose that due to clock skewand setup, pipelining the machine adds1 nano seconds overhead to the clock. Howmuch speed up in the instruction executionrate will we gain from a pipeline?

Consider the unpipelined machine with 10 nano seconds clock cycles. It uses four cycles for ALU operations and branches whereas five cycles for memory operation. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose that due to clock skew and setup, pipelining the machine adds 1 nano seconds overhead to the clock. How much speed up in the instruction execution. rate will we gain from a pipeline?

Consider the unpipelined machine with 10 nano seconds clock cycles. It uses four cycles for ALU operations and branches whereas five cycles for memory operation. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose that due to clock skew and setup, pipelining the machine adds 1 nano seconds overhead to the clock. How much speed up in the instruction execution. rate will we gain from a pipeline?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Let's assume that there are three processors, Pa, Pb, and Pc, like below. You can assume 1-way superscalar, no hyper-threading, and no pipelined for all processors. Pa: 4 GHz clock rate, CPI: 2.2 Pb: 3 GHz clock rate, CPI: 1.5 Pc: 2.5GHz clock rate, CPI: 1.05.1. Show each processors' performance in terms of instruction per second.
Suppose without pipelining, a processor takes 100sec to complete execution of 05 instructions, assuming each instruction require same amount of time for execution. If we can have 5 stage ideal pipeline for the same processor, then How much time will it take to complete execution of these 05 instructions? How much speedup we can achieve?
consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the Section I B of "Advanced Systems Concepts", i.e.:  a one clock cycle fetch  a two clock cycle decode  a three clock cycle execute and a 200 instruction sequence: Show your work. 7. o pipelining would require _____ clock cycles: 8. A scalar pipeline would require _____ clock cycles: How high is the increase in speed (percentage) compared to no pipelining? 9. A superscalar pipeline with two parallel units would require ______ clock cycles: How high is the increase in speed (percentage) compared to no pipelining?
Consider two processors P1 and P2. P1 has a clock rate of 2 GHz, average CPI of 0.8, and requires the execution of 5.0 x 10^9 instructions for a given task. P2 has a clock rate of 3 GHz, an average CPI of 1.2, and requires the execution of 6.0 x 10^9 instructions for the same task. Does the processor with the highest clock rate have a better performance? Justify your answer.
Suppose you have a computer that does instruction processing in anatomic way, with a clock cycle of 7ns and one instruction executioncompleted every cycle.You now split the processing into the five stages of the RISC pipeline,and you get required processing times of• IF: 1ns• ID: 1.5ns• EX: 1ns• MEM: 2ns• WB: 1.5nsYou now have added 0.1ns of delay between each of these stages. What’s the clock cycle time of this 5-stage pipelined machine?
Explain with an example how a 6 stage pipeline processor helps in speeding up the program execution as compared to non-pipelined processor. In the following example, find out the instruction pairs which can lead to data hazard in two stage pipeline and justify your answer. 1) MOV AL, 25H 2) MOV CH, 10H 3) MOV [2002H], AL 4) INC CH 5) MOV [2004H], CH 6) ADD DX, CH
Q: Consider three different processors P1, P2, and P3 that support the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. (a) Which processor has the highest performance expressed in instructions per second? Show your calculations. (b) If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions for each processor. (c) We are trying to reduce the execution time by 30% (i.e., execution time is reduced from 10 seconds to 7 seconds). However, this leads to an increase of 20% in the CPI. For each processor, what clock rate should we have to get this time reduction? (Show the calculations you did to answer this question.)
Assume a 5-stage pipelined CPU (IF – ID – MU– EX – WR) requires following time for differentsections: Pipeline stages ----Required time Fetch Unit ---15 nsDecode Unit ---10 nsMemory Unit---- 20 nsExecution Unit---- 8 nsWrite back Unit ----15 ns The maximum delay required to transfer contents from one state to another is 2ns.a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume thatInstruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions:7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU readonly one data from RAM or save only one data to RAM at a time. Calculate the execution timefor the first 10 instructions of a program as well. Assume the condition is evaluated TRUE.
In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 270 ps 150 ps 240 ps 290 ps 180 ps Also, assume that instructions executed by the processor are broken down as follows: alu beq lw sw 40% 15% 35% 10% 3.0.1 What is the clock cycle time in a pipelined and non-pipelined processor? 3.0.2 Assuming there are no stalls or hazards, what is the utilization of the data memory? 3.0.3 Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles but one instruction finishes before another instruction is fetched. In this organization, an instruction only goes through stages it actually needs (e.g. ST only takes 4 cycles because it does not need the WB stage). Compare clock cycle times and execution times with…
Consider three different processors P1, P2, and P3 executing the same instructionset. P1 has a 3GHz clock rate and a CPI of 1.5. P2 has a 2.5GHz clock rate and a CPI of 1.0, P3has a 4GHz and a CPI of 2.5.a) Which processor has the highest performance expressed in instructions per second?b) If the processors each execute a program in 5 seconds, find the number of cycles and thenumber of instructions.c) We are trying to reduce the execution time by 20% but this leads to an increase of 15% inthe CPI. What clock rate should we have to get this time reduction?
) We examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 200 ps 300 ps 150 ps 250 ps 200 ps Also, assume that instructions executed by the processor are broken down as follows: alu (i.e. add, sub,…) beq lw sw 45 % 20 % 20 % 15% a.) What is the clock cycle time in a pipelined and non-pipelined processor? b.) What is the total latency of seven LW instructions in a pipelined and non-pipelined processor (assume no stalls or hazards) c.) Assuming there are no stalls or hazards, what is the utilization of the data memory? (Hint) R-type instruction: IF ID EX MEM WB: no data memory access required beq: no data memory access required lw: IF ID EX MEM WB: data memory access required sw: IF ID EX MEM WB: data memory access required % of lw + % of sw = ?
Consider two processors P1 and P2. P1 has a clock rate of 2 GHz, average CPI of 0.8, and requires the execution of 5.0 x 10^9 instructions for a given task. P2 has a clock rate of 3 GHz, an average CPI of 1.2, and requires the execution of 6.0 x 10^9 instructions for the same task. Using the above CPI and clock rates of P1 and P2, determine the number of instructions that P2 can execute in the same time that P1 needs to execute 10.0 x 10^9 instructions.