b. Design and reflect on a suitable pipeline technique using which time taken for executing all 3 programs can be further improved. Calculate the improved time using this method by considering that instruction require same number of steps to complete and time taken for each step is same and time gap between each steps is also same? Program A Program B Program C Instruction 1 Instruction K Instruction 5 Instruction 2 Instruction L Instruction 6 Instruction 3 Instruction M Instruction 7 Instruction 4

b. Design and reflect on a suitable pipeline technique using which time taken for executing all 3 programs can be further improved. Calculate the improved time using this method by considering that instruction require same number of steps to complete and time taken for each step is same and time gap between each steps is also same? Program A Program B Program C Instruction 1 Instruction K Instruction 5 Instruction 2 Instruction L Instruction 6 Instruction 3 Instruction M Instruction 7 Instruction 4

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Description: b. Design and reflect on a suitable pipeline technique using which time taken for executing all 3 programs can be further improved. Calculate the improved time using this method by consideringthat instruction require same number of steps to complete

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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If the execution time of pipeline instruction execution is not balanced, what inefficiency must be introduced to allow the piplelined execution to occur? Describe this inefficiency.
Is it still feasible to accomplish pipelined execution even if the time it takes to execute pipeline instructions is not balanced? Where can you perceive the inefficiencies in this situation?
Is it possible to achieve piplelined execution if the execution time of pipeline instruction execution is not balanced? What inefficiency do you see here?
Question 3 Assuming a program with no branch instructions but with a lot of memory access instructions, will this new pipeline harm performance? (Y/N) Please detailed explanation Full explain this question and text typing work only Don't copy and paste before solution
Why is a single instruction in a pipeline datapath not shorter than that in a multi-cycle datapath even though totally a pipeline mechanism performs better. Please select the correct choice. a - Because of quicker time of execution of large number of instructions b - Because pipelined CPUs generally work at a higher clock frequency than the RAM clock frequency, c - Because it is possible to execute multiple instructions sequentially d - Because in a pipeline architecture, 1 instruction abandons the pipeline in each cycle, so the CPI will be of 1. e - Because increase in the number of pipeline stages increases the number of instructions executed simultaneously.
Can pipelined execution be attained if the times at which individual pipeline instructions run are not equal? Exactly what inefficiency have you noticed?
Question 7: Suppose in a program there are 300 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the efficiency of pipeline parallel processing.
ANSWER THE QUSTIONS THAT IS WRITEN OR ON THE PICTURE PLEASE Question 6: Suppose in a program there are 120 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the speedup of pipeline parallel processing. Question 7: Suppose in a program there are 300 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the efficiency of pipeline parallel processing. Question 8: Consider a 5-stage instruction execution in which, Instruction fetch = ALU operation = Data memory access = 250 ps; and Register read = Register write = 200 ps. Find out the speedup factor for pipelined execution.
What is the definition of "instruction pipelinelining"? Provide the remedies in addition to discussing the data discrepancies and branch conflicts.
The runtimes of the five stages of executing an instruction in a non-pipelined machine are listed below. Instruction Fetch 100ps Instruction Decode 200ps ALU 300ps Memory 300ps Write Back 200ps This is then converted into a pipelined machine M1 using the most critical stage as the cycle time. For a new machine M2, we are allowed to break up exactly one stage into two substages of equal times giving us a six stage pipeline. A1: Discuss in short clear sentences the latency differences between the machines M1 and M2. A2: Discuss in short clear sentences the throughput differences between the machines M1 and M2.
It is possible to design compilers and assemblers to order assembly language instructions such that a pipeline is exposed to the least amount of risk possible. One of the objectives of pipeline design is this. Do all assemblers and compilers rearrange instructions provided in assembly language in the same manner to achieve the best degree of productivity?
Q. What is the baseline performance (in cycles, per loop iteration) of the code sequence in if no new instruction’s execution could be initiated until the previous instruction’s execution had completed? Ignore front-end fetch and decode. Assume for now that execution does not stall for lack of the next instruction, but only one instruction/cycle can be issued. Assume the branch is taken, and that there is a one-cycle branch delay slot. Latencies beyond single cycle: Latencies beyond single cycle:Memory LD +6Memory SD +4Integer ADD, SUB +1Branches +2fadd.d +4fmul.d +6fdiv.d +10Execution codeLoop : fld f2, 0(Rx)I0: fdiv.d f8, f2, f0I1: fmul.d f2, f6, f2I2: fld f4, 0(Ry)I3: fadd.d f4, f0, f4I4: fadd.d f10, f8, f4I5: fsd f10, 0(Ry)I6: addi Rx, Ry, 8I7: addi Ry, Ry, 8I8: sub x20, x4, RxI9: bnz x20, Loop Q. Think about what latency numbers really mean—they indicate the number of cycles a given function requires to produce its output. If the overall pipeline stalls for the latency cycles of…