The design team for a simple, single-issue processor is choosing between a pipelined or non-pipelined implementation. Here are some design parameters for the two possibilities: Non-pipelined Version Pipelined Version 500 MHz Parameter 350 MHz Clock Rate Total number of instructions 1000 1000 CPI for ALU instructions CPI for Control instructions CPI for Memory instructions 2.7 1 For a program with 20% ALU instructions, 10% control instructions and 70% memory instructions. Calculate an average CPI for each case? a. b. Which design will be faster according to MIPS?

The design team for a simple, single-issue processor is choosing between a pipelined or non-pipelined implementation. Here are some design parameters for the two possibilities: Non-pipelined Version Pipelined Version 500 MHz Parameter 350 MHz Clock Rate Total number of instructions 1000 1000 CPI for ALU instructions CPI for Control instructions CPI for Memory instructions 2.7 1 For a program with 20% ALU instructions, 10% control instructions and 70% memory instructions. Calculate an average CPI for each case? a. b. Which design will be faster according to MIPS?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Suppose we had a processor design with 5 stages where each stage takes the following amount of time: IF: 400 ps ID: 200 ps EX: 300 ps MEM: 500 ps WB: 200 psQ1: If you choose a pipelined design, what is the CPI? Assume that we have enough instructions such that the brief ramp up period at the beginning and the ramp down period at the end with less than 100% utilization does not matter. Q2: If you choose a pipelined design, what is the average execution time per instruction in picoseconds?
You are designing a floating point coprocessor which will execute floating point instructions 5 times as fast as the regular processor with zero overhead. Given a workload that contains 25% floating point instructions, what is the speedup achieved by adding the coprocessor to the system? Please give the speedup with exact precision.
Suppose you have a computer that does instruction processing in anatomic way, with a clock cycle of 7ns and one instruction executioncompleted every cycle.You now split the processing into the five stages of the RISC pipeline,and you get required processing times of• IF: 1ns• ID: 1.5ns• EX: 1ns• MEM: 2ns• WB: 1.5nsYou now have added 0.1ns of delay between each of these stages. What’s the clock cycle time of this 5-stage pipelined machine?
We begin with a computer implemented in single-cycle implementation. When thestages are split by functionality, the stages do not require exactly the same amount of time. The originalmachine had a clock cycle time of 7 ns. After the stages were split, the measured times were IF, 1 ns; ID,1.5 ns; EX, 1 ns; MEM, 2 ns; and WB, 1.5 ns. The pipeline register delay is 0.1 ns. b) [15]<C.2> If there is a stall every four instructions, what is the CPI of the new machine?c) [10]<C.2> What is the speedup of the pipelined machine over the single-cycle machine?d) [10]<C.2> If the pipelined machine had an infinite number of stages, what would its speedup be overthe single-cycle machine?
For all the questions in this assignment, you should use conditional execution of branch instructions only (i.e., do not use conditional execution of data processing instruction or other non-branch instructions). Question #1 . For each of the following C++-like pseudo code segments, write equivalent ARM assembly language instructions. if (r1 >= 10) { r2 = r2 - r1; } r2 = r2 + 60; if (r4 < 0) r4 = r4 + 100; else r4 = 100 - r4; if (r5 == r6) r5 = r5 + 80; else if (r5 < r6) r5 = r5 - 40; else if (r5 != r8) r5 = -r5; else r5 = 9*r5;
A complete 6-stage non-pipelined 16-bit CPU architecture include 6 components: a register file, a decoder, an ALU, a control unit, a program counter, and ram/memory. Brief overview: opcode is 4 bits 14 different instructions implemented 8 general purpose registers RRR-type instructions are the largest, and take up 9 bits in register addresses 1 bit is a condition bit 2 bits unused simulated clock runs at a 10ns period or 100Mhz simulated memory is 512 bytes Referring to the 3 components as in the picture, namely the File Register, Decoder and ALU, you are required to describe how the three components operate.
Discuss the limitations and trade-offs in increasing the pipeline depth in a CPU. What factors should be considered when determining the optimal pipeline depth?
It is feasible to set up a compiler for assembly language and an assembler in such a way that a pipeline is exposed to the least amount of danger imaginable. One of the goals of pipeline design is to do this. To reach the highest possible level of productivity, do all assemblers and compilers rearrange the instructions that are delivered in assembly language in the same way?
Yes, even if pipeline instructions take a different amount of time to execute at different times. Where can the problems with this situation be found?
Explore the concept of speculative execution and its role in reducing pipeline stalls. Provide examples of how speculative execution is implemented in modern CPUs.
It is feasible to set up a pipeline with the least amount of vulnerability using an assembly-language compiler and an assembler. This is one of the goals of pipeline design. When given assembly language code, do all assemblers and compilers reorder the instructions in the same way to maximize efficiency?
What are the trade-offs involved in increasing the depth of a pipeline in a CPU design?