Consider a 32-bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has?
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- Take the multiprocessor with 30 processors, each processor is capable od max2Gflops. What is the maximum capability of the multiprocessor for the execution of anapplication that has 5% sequential code?Computer Science 1 .Consider the task of doubling all the elements of a 8192 element vector, which might be done on a SISD machine by the following code. Suppose each iteration of the loop requires 20 clock cycles - so the whole process needs 163,840 clocks. for (int i = 0; i < 8192; i ++) x[i] *= 2.0; Now suppose, instead, that the process is done on a pipelined processor having a single pipeline that supports memory to memory vector operations. Assume that each computation (fetch x[i], double it, store result) still takes 20 clock cycles, but that the pipeline, once full, can produce one result each cycle. How many clock cycles total will be needed for this case?Computer Architecture (Already submit this question, but I think I got wrong solution) Consider a computer that has a number of registers such that the three registers R0 =1500, R1 = 4500, and R2 = 1000 Show the effective address of memory and the registers’ contents in each of the following instructions 1. ADD (R1), R2 2. MOVE 500(R0), R2 3. ADD (40), R1 4. SUBTRACT (5000), R2 5. ADD #30, R2
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- A 32-bit computer has 32 registers, and a memory addressed by bytes with two cycles for reading and writing operations. Consider the instruction ADD, R1, addr. This instruction adds the value stored in R1 to the value stored in the memory address addr, and stores the result in the register R1. a) Show a possible format for this instruction, having into account that the computer has 100 machine instructions and the addresses are represented using 32 bits. b) Indicate the elemental operations and control signals needed to execute the previous instruction.2. Suppose we have two implementations of the same instruction set architecture.Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some programand computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the sameprogram. Which computer is faster for this program and by how much?Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?
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