Consider a pipelined system with four stages: IF, ID, EX, WB. Following chart shows the clock cycles required by instruction to complete each stage. Writ tructions Fetch(IF)Decode(ID) Execute(EX) back( 10 1 1 2 1 11 2 3 1 12 2 2 13 1 1 1 14 3 1 How many clock cycles are required to complete the instructions?

Consider a pipelined system with four stages: IF, ID, EX, WB. Following chart shows the clock cycles required by instruction to complete each stage. Writ tructions Fetch(IF)Decode(ID) Execute(EX) back( 10 1 1 2 1 11 2 3 1 12 2 2 13 1 1 1 14 3 1 How many clock cycles are required to complete the instructions?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Consider a multilevel computer in which levels are vertically stacked, with the lowest level being level 1. Each level has instructions that are m times as powerful as those of the level below it; that is, one level r instruction can do the work of m instructions at level r-1. However, n instructions at level r-1 are required to interpret each instruction at level r. Given this, answer the following questions: If a level 1 program requires k seconds to run, how long would the equivalent program take to run at levels 2, 3 and 4. Express your answer in terms of n, m, and r. What is the performance implication for the program if n > m? Conversely, what is the implication if m > n? Which case do you think more likely? Why?
Suppose you have a computer that does instruction processing in anatomic way, with a clock cycle of 7ns and one instruction executioncompleted every cycle.You now split the processing into the five stages of the RISC pipeline,and you get required processing times of• IF: 1ns• ID: 1.5ns• EX: 1ns• MEM: 2ns• WB: 1.5nsYou now have added 0.1ns of delay between each of these stages. What’s the clock cycle time of this 5-stage pipelined machine?
Suppose an instruction takes four cycles to execute in a nonpipelined CPU: one cycle to fetch the instruction, one cycle to decode the instruction, one cycle to perform the ALU operation, and one cycle to store the result. In a CPU with a four-stage pipeline, that instruction still takes four cycles to execute, so how can we say the pipeline speeds up the execution of the program?
A CPU has an instruction pipeline with the following 4 segments. 1.F1(Fetch Instruction) 2.DA(Decode, Address) 3.FO(Fetch Operand) 4.EX(Execution) D1: Add R1,R2 //R1=R1+R2 Add R4,R1 //R4=R4+R1 Add R4,R3 //R4=R4+R3 Cmp R4,R5 // compare R4 and R5 Jg D1 //if Jump Greater (if R4>R5) Sub R2,R1 //R2=R2-R1 Sub R2,R3 //R2=R2-R3 Jmp D1
A hypothetical processor has 9 stages of a pipeline as shown in the table below. The first row in the table below shows the pipeline stage number, second row gives the name of each stage, and third row gives the delay of each stage in Nano-seconds. The name of each stage describes the task performed by it. Each stage takes 1 cycle to execute. This processor stores all the register contents in a compressed fashion. After fetching the operands the operands are first decompressed, and before saving the results in register file, the results are first compressed. a)How many cycles are required to execute one instruction on this pipeline? b)How many cycles are required to execute 19 instructions on this pipeline? Assume that no stall cycles occur during the execution of all instructions. c) Assume that all necessary bypass/forwarding circuitry is implemented in this 9 stage pipeline. How many cycles will the pipeline stall during the execution of below given two instructions? Briefly explain…
Consider the two back to back instructions: lw $s1, 24($t3) add $t2, $s1, $t1 In the standard five stage, pipelined machine, consider the above two instructions where the second instruction tries to read a register that is being written to by the first instruction which is a 'load word' (lw) command. The scheduler has not done any juxtaposing of the commands. a. There will be no hazard situation as the load word deals with the data memory and the read is from the registers. b. There will be no hazard situation, since the read is from the same location where the write is taking place. c. It is possible to avoid a bubble in the flow by forwarding from the write back stage. d. It is not possible to avoid Data Hazard issues here and inserting a bubble is a way out of this issue.
Let's assume that there are three processors, Pa, Pb, and Pc, like below. You can assume 1-way superscalar, no hyper-threading, and no pipelined for all processors. Pa: 4 GHz clock rate, CPI: 2.2 Pb: 3 GHz clock rate, CPI: 1.5 Pc: 2.5GHz clock rate, CPI: 1.05.1. Show each processors' performance in terms of instruction per second.
consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the Section I B of "Advanced Systems Concepts", i.e.:  a one clock cycle fetch  a two clock cycle decode  a three clock cycle execute and a 200 instruction sequence: Show your work. 7. o pipelining would require _____ clock cycles: 8. A scalar pipeline would require _____ clock cycles: How high is the increase in speed (percentage) compared to no pipelining? 9. A superscalar pipeline with two parallel units would require ______ clock cycles: How high is the increase in speed (percentage) compared to no pipelining?
1. Consider the operation of a machine with the data path of the figure below. Let us call thismachine "Teletraan-1". Teletraan-1 has no pipeline. Suppose that fetching an instruction takes4 nsec, decoding an instruction takes 1 nsec, fetching the operands from memory or registersto ALU takes 2 nsec, running the ALU takes 2 nsec, storing the result back to the destinationregisters takes 1 nsec.How much time does Teletraan-1 need to execute 1 million instructions?A. 1 nsec x 1 million = 0.001 secondB. 2 nsec x 1 million = 0.002 secondC. 4 nsec x 1 million = 0.004 secondD. 10 nsec x 1 million = 0.01 second 2. Since the above machine Teletraan-1 has no pipeline, an instruction must be completed in oneCPU clock cycle. As a result, a CPU clock cycle must be longer than or equal to the executiontime of one instruction. To improve it, we developed "Teletraan-2". Teletraan-2 has a fivestage pipeline. It takes 5 nsec to fetch an instruction, 2 nsec to decode an instruction, 3 nsec tofetch…
True/False Run times of the typical five stages to execute an instruction are as given in some units of time: Instruction Fetch: 10 Instruction Decode: 15 Execute: 30 Memory: 50 Write Back: 20 If this is implemented as a pipelined versus a non-pipelined machine, then depending on the absence of hazards, one could expect the speedup to be about 2.5.
The following sequence of instructions are executed in the basic 5-stage pipelined processor OR R1, R2, R3 OR R2, R1, R4 OR R1, R1, R2 a) Indicate the dependencies and their types b) Assume no forwarding in this pipelined processor indicate hazards and NOP instruction to eliminate them. c) Assume there is full forwarding, indicate hazards and NOP instructions to eliminate them
Consider a fairly standard 5-stage pipeline: Fetch; Decode; Execute; Memory; Writeback. Let the processor be a nice, simple RISC single-cycle machine. The instructions below are executed. The branch should be taken — however, this processor does no prediction and always assumes a fall-through. Draw a Gantt chart for this and determine the branch penalty. SUB R1, R1, #1 BEQ R1, R0, LoopDone LOAD R2, Memory(100) SUB R3, R2, R1 MUL R3, R3, R3 LOAD R4, Memory(200) ADD R5, R4, R3 STORE R5, Memory(204)