Quesion:Show the execution of your program on the above pipelined processor for k = 6 by drawing a diagram. Assume that the fetched and decoded instructions are stored in an instruction window IW with unlimited capacity (and so you can store any number of instruction in the IW). Explain where and why delay slots Assume that the processor can do out-of-order execution to speed up the completion of the program. Assume that there is only one bus, and that the fetching of instructions uses this bus. So the fetching of an instruction can conflict with a stage where an instruction accesses memory. A Instruction Set ArchitectureA.1 Instruction setWe present a list of instructions typical of a RISC (reduced instruction set computer) machine. In data-movement and control instructions, the addresses may be immediate #X, direct (memory) M, indirect (memory) [M], register r, or register indirect [r] addresses. Data-processing instructions use immediate or register addressing. PC is the programme counter and a <- b indicates that the value of b is placed in a. LOAD a, b a <- bSTOR a, b a <- bADD a, b, c a <- b + c ASH a, b, c a <- (b >>[s] c)LSH a, b, c a <- (b >>[u] c) BR a PC <- a SUBa,b,ca<-b- cBEQa,b,cPC<-aifb =cMULa,b,ca<-b* cBNEa,b,cPC<-aifnotb = cDIVa,b,ca<-b/ cBLTa,b,cPC<-aifb <cANDa,b,ca<-b& cBGTa,b,cPC<-aifb >c OR a, b, c a <- b | cNOT a, b a <- !b BLE a, b, c PC <- a if b <= c BGE a, b, c PC <- a if b >= c Note: Here b >>[s] c denotes the arithmetical shift of b to the right by c positions, andb >>[u] c denotes the logical shift of b to the right by c positions. A.2 The pipelineWe will use a five-stage pipeline:IF (instruction fetch),ID (instruction decode),RR (register read),EX (execute instruction),WB (write back result into register).Note that for some instructions (e.g., LOAD r, #X) some of the pipeline stages (e.g., RR) are not A.3 Execution rulesThe rules for the execution of instructions are as follows:All instructions go through the IF and ID stagesFor data-movement instructions the data transfer between the CPU and main mem- ory happens in the execute stage. (This means that if a data transfer operation is executing, no data can be transferred across the main-memory )Immediate addressing for input arguments does not require RR or EX (e.g., LOAD r1, #X).Arithmetic and logic instructions need RR, EX andBranching operations require RR, EX and WB, unless all operands are immediate, in which case only EX and WB areFor the instruction LOAD a, b the argument b must be an immediate address or memory location and a must be aFor the instruction STOR a, b the argument b must be an immediate address or register and a must be a memoryFor each of the remaining instructions the arguments a, b and c must all be registers or immediateYou may assume for the sake of the questions that the ISA supports floating point arithmetic with no loss of precision Questions1. The function L is defined as L(1) = 2,L(2) = 1,1(3) = 3,L(4) = 4 and for n 2 4,Lin) + L(n – 1) + L(n – 2)Ytn + 11Lin - 3)i.e., the (n + 1}-th value is given by the sum of the n-th, n-1-th and n– 2-thvalues divided by the n-3-th value.(a) Write an assembly program for computing the k-th value Lik), where k isan integ er bigger than 4 and read from a memory location M, and storing L(k)at memory location M. Use the instruction set in the Instruction SetArchitecture described in Appendix A.(b) Consider a pipelined processor, where the pipeline stages are thosedescribed in the appendix. Describe what ha ppens in the pipeline stagesfor the various types (data movement, data processing, control) ofinstructions.(c) Show the execution of your program on the above pipelined processor for k= 6 by drawing a diagram. Assume that the fetched and decoded instructionsare stored in an instruction window IW with unlimited capacity (and soyou can store any number of instruction in the IW). Explain where and whydelay slots appear.execution to speed up the completion of the program. Assume that thereis only one bus, and that the fetching of instructions uses this bus. So thefetching of an instruction can conflict with a stage where an instruc tionAssum e that the processordo out-of-ordercanaccesses memory.

Assembly language program is defined as the low-level programming language for a computer or other…

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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A Instruction Set Architecture

A.1 Instruction set

We present a list of instructions typical of a RISC (reduced instruction set computer) machine. In data-movement and control instructions, the addresses may be immediate #X, direct (memory) M, indirect (memory) [M], register r, or register indirect [r] addresses. Data-processing instructions use immediate or register addressing. PC is the programme counter and a <- b indicates that the value of b is placed in a.

LOAD a, b a <- b

STOR a, b a <- b

ADD a, b, c a <- b + c

ASH a, b, c a <- (b >>[s] c)

LSH a, b, c a <- (b >>[u] c) BR a PC <- a

SUB

- c

BEQ

b =

MUL

* c

BNE

not

b = c

DIV

/ c

BLT

b <

AND

& c

BGT

b >

OR a, b, c a <- b | c

NOT a, b a <- !b

BLE a, b, c PC <- a if b <= c BGE a, b, c PC <- a if b >= c

Note: Here b >>[s] c denotes the arithmetical shift of b to the right by c positions, and

b >>[u] c denotes the logical shift of b to the right by c positions.

A.2 The pipeline

We will use a five-stage pipeline:

IF (instruction fetch),
ID (instruction decode),
RR (register read),
EX (execute instruction),
WB (write back result into register).
Note that for some instructions (e.g., LOAD r, #X) some of the pipeline stages (e.g., RR) are not

A.3 Execution rules

The rules for the execution of instructions are as follows:

All instructions go through the IF and ID stages
For data-movement instructions the data transfer between the CPU and main mem- ory happens in the execute stage. (This means that if a data transfer operation is executing, no data can be transferred across the main-memory )
Immediate addressing for input arguments does not require RR or EX (e.g., LOAD r1, #X).
Arithmetic and logic instructions need RR, EX and
Branching operations require RR, EX and WB, unless all operands are immediate, in which case only EX and WB are
For the instruction LOAD a, b the argument b must be an immediate address or memory location and a must be a
For the instruction STOR a, b the argument b must be an immediate address or register and a must be a memory
For each of the remaining instructions the arguments a, b and c must all be registers or immediate
You may assume for the sake of the questions that the ISA supports floating point arithmetic with no loss of precision