Consider the following linear block code: Each codeword consists of 3 data bits and 3 parity check bits, i.e., [i,,i2,i3,PuP2, P3]- The parity check bits are defined by P1 = i1 + iz P2 = i1 + iz mod 2 P3 = i2 + iz mod 2 mod 2 a. Determine the generator matrix. b. List all the legitimate codewords. c. Determine the minimum distance. d. Suppose that a single error occurs at the first bit. Compute the syndrome. Similarly, compute the syndrome for a single error at each of the other bits. e. Suppose that at most one error occurs. Correct the received vector [010001] by syndrome decoding.

:CLO1.2:Assume having the following value in register A= 0110 1100, Give the logical operations along with the appropriate mask to achieve the following Note: The bits are numbered starting from 0 to 7 from right to left AND, 1000 1000 .A Selectively complements bits number 1st and 3rd bits AND , 0000 1111 .B Clear the higher portion of A v OR, 1000 1000 .C Set the sign bit to 1 v XOR , 0000 1010.D Set the 3rd and 7th bit to 1 OR, 0000 1010 .E OR,1000 0000 .F

Assume that the system has eight 2-bit data inputs, A=a1a0, B=b1b0, C=c1c0, D=d1d0, W=w1w0, X=x1x0, Y=y1y0, Z=z1z0. There are also 2 control bits s1s0. The system computes A+B, C+D, W+X, and Y+Z when s1s0 equal to `11', `10', `01', `00', respectively. Use 1-bit 2-to-1 multiplexers and a 2- bit adder to implement this function. Please show how the inputs, multiplexers, and adder are connected. Label the inputs and select signals clearly. You don't need to show the details of the adder. (Hint: The adder has two 2-bit inputs E=e1e0 and F=f1f0. Each of E and F is generated by a 2-bit 4-to-1 multiplexer, which can be built using 1-bit 2-to-1 multiplexers.)

Needs Complete solution with 100 % accuracy.