Design a combinational logic circuit to obtain the following functionality. Using the input as Opcode and the output as QA which is then stored using an 8-bit Register made of simple D- Type flip flops which are evaluated on the rising edge of the clock. The register has a synchronous reset. Use Xilinx Vivado to build a VHDL circuit to perform this function. Your code must be properly commented. Please use VHDL code Opcode 000 001 010 011 100 101 110 111 Logic Function Q=A OR not(B) Q = B Q = not(A) AND B Q = not (B) Q = not(A XOR B) Q = not(A) Q = Q = not(A OR B) Q = (A OR "11001101")

We can design ripple counter that counts from 0 – 10 by inserting (A3, A1) to NAND gate and connect the output of the NAND gate to input, where as the data input is"0000" A3 A2 A1 AO CLR Load 4- bit counter CLK Count Data load inputs load count CLK CLR

For the 74ALS138 logic circuit shown in the figure below, answer the following questions: 1- Find the truth table of the 74ALS138 logic circuit. 2- Indicate the states of the 74ALS138 outputs for each of the following sets of inputs. a) E3 E21, E₁ = 0, A₂ = A₁ = 1, A₁ = 0 b) E3 = 1, E2= E₁ = 0, A₂ = 0, A₁ = A0 = 1 A2 A₁ Ao Ē₁ Ē₂ E3 299 74ALS138 1-of-8 decoder E 1407 06 05 04

Design a combinational circuit that detects an error in the representations of a decimal digit in Binary Coded Decimal (BCD). In other words, obtain a logic diagram for a circuit that accepts the four BCD bits as input and whose output is when the inputs contain any one of the six unused bit combinations in the BCD code.

Design a 2-bit modulo 8 synchronous counter in Multisim and implement the design using two 74LS112 IC JK flip flops based on this circuit. Use word generator and logic analizer as shown.

= 0, Design a sequential circuit with two D flip-flops A and B, and one input x_in. When x_in the state of the circuit remains the same. When x in = 1, the circuit goes through the state transitions from 00 to 01, to 11, to 10, back to 00, and repeats.

need help with digital logic

Synchronous and asynchronous inputs for flip-flops with example : Output to be displayed on DSO   pls do it on multisim

Design an asynchronous sequential logic circuit which has inputs (X1 and X2) and one output (Z) the output (z) must go to (1) when at the end of the input sequence (00,10), This output must be maintained (unchanged) for all inputs change until the sequence (11,10) occurs, then the output must go to zero (0). and The output flips when the input is (01,10)