Effective overlap of operations of CPU and I/O devices, requires a proper mix of a. I/O bound jobs b. CPU bound jobs c. Memory bound jobs d. Balance of CPU and I/O jobs
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| 471. | Effective overlap of operations of CPU and I/O devices, requires a proper mix of |
| a. | I/O bound jobs |
| b. | CPU bound jobs |
| c. | Memory bound jobs |
| d. | Balance of CPU and I/O jobs |
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- q) How the operation of software interrupt instructions differs i.e. INT, INTO, INT 3, and BOUND? q) Dynamic RAM (DRAM) retains data for only a short period (usually 2–4 ms) creatingproblems for the memory system designer. What type of mechanism is required to overcome this problem in DRAMs? q) What are the three common methods of expanding the interrupt structure of themicroprocessor? Explain any one of them along with example.1.16 Direct memory access is used for high-speed I/O devices in order to avoid increasing the CPU's execution load. a. How does the CPU interface with the device to coordinate the transfer? b. How does the CPU know when the memory operations are com¬ plete? c. The CPU is allowed to execute other programs while the DMA controller is transferring data. Does this process interfere with the execution of the user programs? If so, describe what forms of interference are caused.1.Which of the following leads to slow-down of file reads? * a)Excessive long-term usage of hard disk b)Disk caches c)Fragmentation of files d)Aging mechanical head 2.The main reason why interrupts are often not disabled in interrupt handling is because: * a)It is not supported by all CPU architectures. b)Because disabling interrupts is often not an atomic operation. c)So as to allow a single interrupt handler to handle interrupts from various devices. d)For more system responsiveness, we require preemptive interrupt handling.
- -What is the fastest type of memory available on a digital computer system? Explain why this particular type ofmemory has to be faster than other types of memory. - Would a computer's hard drive be an example of primary or auxiliary memory? Explain your answer.- Explain why an to interrupt request (IRQ) conflict could cause a sound card to stop working correctly and theprocedures for fixing such an IRQ conflict.Which hardware methods optimize virtual memory systems? Functioning how? Provide two examples.1- define the following:Clock rateInstruction setBandwidthParallelism.CMOS TechnologyEmbedded systems1)What are the differences between RAM and ROM and what is the control unit in 8086 and its function?2_what is the ALU and its function?5- What physical address is represented by: (a)4370:561EH (b) 7A32:0028H
- QUESTION TWO (2) There are three types of access which are sequential access, direct access, and random access. a) Analyze the differences between THREE (3) of the memory access types b) State the general relationship between access time, memory cost, and capacity3. The advantage of I/O mapped devices to memory mapped is a. The former offers faster transfer of data b. The devices connected using I/O mapping have a bigger buffer space c. The devices have to deal with fewer address lines d. No advantage as suchChange your Virtual Memory pagefile to the following capacity: Initial Size: 10MBMaximum size: 250MBNB: Do not apply your changes. (9)Instructions:- Provide all necessary steps to accomplishing the tasks above.- Upon successful completion, provide screenshots of your created Virtual Memory pagefile.
- The laptop in question is an Intel i7-8750H 64-bit. Fill up the blanks with detailed information on the following subjects. Content: memory standards, which include: (a) Distinctions between RAM and ROM, (b) Explain what cache memory is and why it is crucial. (c) The number and size of L1, L2, and L3 caches (if appropriate). (d) Cache type (direct mapping, or associative), (e) Addressing Style (byte, or block), (f) Support for virtual memory (may be dependent on OS type)A given computer has a single cache memory (off-chip) with a 2 ns hit time and a 98% hitrate. Its main memory has 40 ns access time.i. What is the computer’s effective access time? ii. If an on-chip cache with a 0.5 ns hit time and a 94% hit rate is added to it, what isthe computer’s new effective access time? iii. How much of a speedup does the on-chip cache give the computer?10. Q1 : What is an atomic instruction? Show that if the wait operation is not executed atomically, then mutual exclusion may be violated Q2: What is spinlock? Discuss the advantage and disadvantage of using spinlock. Why do you think Solaris, Linux, and Windows 2000 use spinlocks as a synchronization mechanism only on multiprocessor systems and not on single- processor systems?