For a processor with 32-bit bus width and address bus width, set-associative cache memory will be designed. For the 2-way set-associative cache with a capacity of 16 KByte and a block size of 16 bytes, determine how many bits the tag, index, word offset and Byte Offset fields of the processor address path should be. A 20 bit, 8 bit, 2 bit ve 2 bit B 20 bit, 9 bit, 2 bit ve 1 bit 19 bit, 9 bit, 2 bit ve 2 bit D 19 bit, 8 bit, 3 bit ve 2 bit

As the MIPS stack grows in size when more items are push onto it, the $sp register will O contain increaseing memory address values O contain decreasing memory address values

For the below microprogrammed architecture, what is the ALU sequence of actions/micro instruction code: ALU(F2,F1,F0) required to implement the instruction SUB DO, D1,#1? Assume that CL1 =0 for Latch 1 and CL2 =1 for Latch 2 Note: The table below defines the effect of the ALU's function code. Bus A Bus B Guen Read Write Data out Main store TE Guow wData in The memory performs a read when Read 1 TEus Address and a write when Write = 1 Cuan MAR Curn Gvern F2 F1 FO Operatlon MBR Copy P ta bus A A=P G. Gr IR 1 Copy Q to bus A A = Q Grc Copy P+1 to bus A A =P+1 PC 1 TE Gọo Cp 1 1 Copy Q+1 to bus A A = Q+1 DO 1 Copy P- 1 to bus A A =P -1 Co Got D1 1 Copy Q - 1 to bus A A =Q 1 TEO 1 1 Copy bus P +Q to bus A A =P+Q ALU P f(PO) A =P - Q Latch 1 1 Copy bus P Q to bus A t O Latch 2 Function select F, F, Fo F2F1F0=111 O F2F1F0=100 F2F1F0=101 O F2F1F0=010

Computer Architecture Consider the below one-bus organization find the micro-operations at each step for the following instructions: 1- Instruction Load (100), R4 (R4 M[M[100]]) 2- JUMP X, where X is a memory location that contains the address of the instruction to be executed