How would i create this chip in hdl HiLoMux - This has one 8-bit input bus, in, and one 4-bit output bus, out. Also present is a sel input, which is used to select what appears on out. If sel is false, then out should contain the lower 4-bits of in (i.e. in[0], in[1], in[2], in[3]). If sel is true, then out should contain the upper 4-bits of in (i.e. in[4] mapped to out[0], in[5], mapped to out[1], etc.). In other words, the HiLoMux can be used to select a nibble from a byte… We’ll use this circuit in a later exercise to enable the 4-bit ALUcore below to do 8-bit operations.

Regarding RISC-V: Considering the case of adding two positive 32-bit integers and placing the result in a 32-bit register:  Under what scenario would there be an overflow? Please show a quantitative example to demonstrate the overflow?  From the example above, how can we detect this overflow?   Since there are 32 bit-wise additions that need to be done for adding these 32-bit integers, this addition operation may be slow. To improve the performance, one straightforward idea is to use 32 1-bit address and do the 32 bitwise additions all at the same time. Do you think this straightforward idea would work (i.e generate correct result and achieve the anticipated performance improvements) and why?

Complete a Verilog code for a 4-bit one-hot counter. Complete "your code here" boxes below (two parts). The "reset" is an active HIGH and will asynchronously_make the output to 4'b1000. 1000 → 0100 → 0010 → 0001→ 1000 → ... repeat!! module four_bit_ohc (clk, reset, q); output [3:0] q; input clk, reset; your code here always @(posedge clk, reset) begin // your code here end endmodule

How does the width of a register relate to the number of D-flip-flops used in the circuit? Each register is implemented with one D-flip-flop, regardless of the width of the register. Each bit in the register corresponds to two D-flip-flops. Each bit in the register corresponds to a D-flip-flop, so it is 1-to-1. Since D-flip-flops have a Q and Qn output, you only need 1 D-flip-flop for each bit in the register.

Solve number 2

o [0.4] 74153 chips have two 4-1 multiplexors, they selector bits, so they are not entirely independent. Why is this beneficial, in our case? What would we have to do if we wanted different selectors for each MUX? al Deliverables: