Problem 1. This problem is about operand modes, in particular about memory addressing using the operand modes described in lecture and the textbook. The following shows the contents of a portion of the program memory (locations Ox10000 through 0x10040), and certain registers. All contents are 64-bit quantities. Address Memory Contents 0x10040 0x10038 0x10030 0x10028 0x10020 0x10018 0x10010 0x10008 100 0x10040 200 25 0x10028 0x10020 500 0x10018 Register Contents %rdi 0x10008 %rsi 0x20 8 4 %rdx %rcx

4. By assuming that 35 is a two digit number, consider memory storage of a 64- bit word stored at memory word 35 in a byte-addressable memory (a) What is the byte address of memory word 35? (b) What are the byte addresses that memory word 35 spans? (c) Draw the number 0XF1234567890ABCDE stored at word 35 in both big-endian and little-endian machines. Clearly label the byte address corresponding to each data byte value.

Translate the following C code to MIPS assembly, assuming that the variables f, g, h, i, and j correspond to registers $50, $s1, $s2, $s3, and $54 respectively. Also, assume that the base addresses of arrays A and B are contained in $56 and $s7 respectively, and that each element of arrays A and B are 4-byte words: B[8] =A[i] + A[j]; Which of the following MIPS assembly code snippets correctly performs the above operation? sll $t1, $s3, 2; add $t1, $56, $t1; lw $12, 0($t1); sll $t1, $s4, 2; add $11, $s6, St1; lw $13, 0($t1); add $12, $12, $t3; sw $12, 32($s7) sll $t1, $s3, 2; add $11, $s6, $t1; lw $12, 0($t1); sll $t1, $s4, 2; add $11, $s6, $t1; lw $13, 0($t1); add $t4, $12, $t3; sll $15, $t0, 2; add $15, $s7, $15; sw $t4, 32($15) Iw $11,0($s3); Iw $12, 0($s4); add $13, $11, $12; sw $13, 32($s7) sll $t1, $s3, 2; lw $12, 0($t1); sll $t1, $s4, 2; lw $13, 0($t1); add $t4, $t2, $t3; sw $t4, 32($s7)

Consider memory storage of a 64-bit word stored at memory word 32 ina byte-addressable memory(a) What is the byte address of memory word 32?(b) What are the byte addresses that memory word 32 spans?(c) Draw the number 0xF1234567890ABCDE stored at word 32 in both big-endianand little-endian machines. Clearly label the byte address corresponding to eachdata byte value.

Q2. For the following assume that values A, B, C, D, E, and F reside in memory. Also assume that instruction operation codes are represented in 6 bits, memory addresses are 64 bits, data size is 32 bits and register addresses are 5 bits. a. For each instruction set architecture shown in Figure A.1, how many addresses or names (including both memory and register), appear in each instruction for the code to compute C = A+ B, and what is the total code size? passor TOS Memory (A) Accumulator (C) Registry (D) Re loed oore Figure A.1 Operand locations for four instruction set architecture classes. The arrows indicate whether the oper and is an input or the result of the orithmetic-logical unit ALU operation, or both an input and result Lighter shoes indicate inputs, and the dark shode indicates the result in a top of stack (TOS) register points to the top input operand, which is combined with the operand below. The first operand is removed from the stack, the result takes the place of the…

Q.8. are missing. The assembler generates a relocatable code. All references use direct addressing. Write the values of the location counter (LC) and the contents of the symbol table, and also fill in the missing references in the machine code. (Assume that 3 bytes are allocated for each instruction and WORD pseudo-operation allocates 3 bytes and stores the given number at that byte.) Given the following assembly language program and its equivalent machine language code where some references START LC Machine code INST1 ЗА 00 00 Symbol Table L1: INST2 D1 D5 ?? ?? JZR L1 7B ?? ?? HLT 4C 00 00 D1: WORD 5 00 00 05 END

Q.1.     A computer uses a memory unit with 1024 K words of 32 bits each (as shown in the figure below). A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part (15). How many bits are there in the operation code, the register code part, and the address part? Draw the instruction word format and indicate the number of bits in each part? How many bits are there in the data and address inputs of the memory?

By assuming 32 is a two digitnumber, consider memory storage of a 64-bit word stored at memory word 32 ina byte-addressable memory.(a) What is the byte address of memory word 32?(b) What are the byte addresses that memory word 32 spans?(c) Draw the number 0xF1234567890ABCDE stored at word 32 in both big-endianand little-endian machines. Clearly label the byte address corresponding to eachdata byte value.

Please solve and show all work. For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 8-byte words: f = (g+i+2) + (h − 8);          B[8] = A[i-9] + A[j+8] + 7;

If random access memory (RAM) and cache memory (both of which are comprised of transistors), then what is the function of cache memory? Do we need several different forms of memory, or can we get by with only one?