Question (4): Build a finite state machine (FSM) with an input X and an output Z. If the sequence '0110' shows up on X, then a value '1' should show up on Z, otherwise '0'. Allow overlap of Sequences (i.e., end of one sequence could be the beginning of another one). Unused states should go to the initial valid state. You need to give two different designs. One for Moore and the other for Mealy. In each design case:- a) Draw the state diagram. b) Write the state stable.

Design a finite state machine (FSM) with one input A and two outputs S and L. The FSM should detect whether a short or a long pulse appears on input A and assert output S in case of a short pulse and assert output L in case of a long pulse. A short pulse is defined as a pulse that lasts up to a single state duration and a long pulse is defined as a pulse that lasts for more than one state transition. Draw the algorithmic state machine (ASM) chart of your FSM design.

Give a regular expression for the set recognized by the finite-state machine and draw the finite-state machine.

A sequential circuit has one input X and four outputs Z₁ Z₂ Z3 Z4. Z1 Z2 Z3 Z4 represents the gray code encoded number equal to the number of pairs of adjacent 1's that have been received as inputs. Use the gray code that is on page 22 of the textbook. For example, if the circuit had received 7 pairs of 1's as inputs, Z₁ Z2 Z3 Z4 = 1011. In addition, the circuit resets when the circuit receives 5 pairs of 1's. Find a Moore state graph and table for the circuit. Examples Input sequence: Output sequences: X = 1 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 10 Z₁ = 0 0 0 0 0 0000000000100 Z₂ 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 Z3 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 - Z4 = 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 X 11111111 Input sequence: Output sequences: Z₁ = 0 0 0 0 0 100 Z2 0 0 0 0 1 100 = Z3 = 0 0 1 1 1 1 0 0 Z4 0 1 1 0 0 0 0 1 =

Given a certain truth table, there is a unique implementation of it using logic gates. True or False? Briefly explain your answer.