Suppose that a processor has access to three levels of memory. Level 1 contain 2000 words and has an access time of 0.02 msec. Level 2 contain 10,000 words and has an access time of 0.2 msec. Level 3 contains 20,000 words and has an access time of 2 msec. Assume that ifa word to be accessed is in level 1, then processor access it directly.is in level 2 the word is first transferred toL, and then accessed by the processor. Similarly for Ly the word is transferred to La then to L, and then accessed. The hit ratio for level 1 is 0.65 and for level 2 is 0.45. What is the average access time (in ?

Suppose that a processor has access to three levels of memory. Level 1 contain 2000 words and has an access time of 0.02 msec. Level 2 contain 10,000 words and has an access time of 0.2 msec. Level 3 contains 20,000 words and has an access time of 2 msec. Assume that ifa word to be accessed is in level 1, then processor access it directly.is in level 2 the word is first transferred toL, and then accessed by the processor. Similarly for Ly the word is transferred to La then to L, and then accessed. The hit ratio for level 1 is 0.65 and for level 2 is 0.45. What is the average access time (in ?

Name: Suppose that a processor has access to three levels of memory. Level
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Description: Suppose that a processor has access to three levels of memory. Level 1 contain 2000 words and has an access time of 0.02 msec. Level 2 contain 10,000 wordsand has an access time of 0.2 msec. Level 3 contains 20,000 words and has an access time of 2

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Suppose a given processor has access to two levels of memory. Level 1 contains 1000 words and has an access time of 0.01 μs; level 2 contains 100,000 words and has an access time of 0.1 μs. Assume that if a word to be accessed is in level 1, then the processor accesses it directly. If it is in level 2, then the word is first transferred to level 1 and then accessed by the processor. For simplicity, ignore the time required for the processor to determine whether the word is in level 1 or level 2. Suppose 95% of the memory accesses are found in level 1, define the hit ratio (H) and find the average access time.
Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz.Computer B has a CPI of 2.5 and can be run at a clock rate of 750 Mhz. Wehave a particular program we wish to run. When compiled for computer A, thisprogram has exactly 100,000 instructions. How many instructions would theprogram need to have when compiled for Computer B, in order for the twocomputers to have exactly the same execution time for this program?
a. We are given a system with 2 levels of cache, L1 and L2. The CPU directly interfaces to the L1 cache, which has a hit time of 1 ns and a hit rate of 0.4. On misses, the L1 accesses the L2 cache, which has an access time of 20 ns, and a hit rate of 0.8. If the L2 misses, it accesses the main memory, which has an access time of 100 ns. Determine the average memory access time, of the CPU to the memory hierarchy.b. A cache is inserted between the main memory, which is 32 MB, and the CPU. This cache can accomodate 64 blocks and each block can accomodate 128 words (2B per word). How many possible blocks can be stored in one cache block if it is a direct-mapped cache?
2. Suppose we have two implementations of the same instruction set architecture.Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some programand computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the sameprogram. Which computer is faster for this program and by how much?
Assume a 3GHz processor executes three classes of instructions(A, B, C).i. Calculate the average CPI for this sequence of program.ii. Calculate the execution time for this sequence of program.iii. If we use a system with four same processors, there will bespeed up by a factor of 4 for classes A and C, but class B willremain unaffected. Calculate the new execution time for thissystem. What is the overall speed up? Class A B C CPI for class 4 2 10 IC in sequence 100 200 300
A certain microprocessor requires either 2, 3, 4, 8, or 12 machine cycles to perform various operations. A total of 25% of its instructions require 2 machine cycles, 20% require 3 machine cycles, 17.5% require 4 machine cycles, 12.5% require 8 machine cycles, and 25% require 12 machine cycles.Q) Suppose this system requires an extra 20 machine cycles to retrieve an operand from memory. It has to go to memory 40% of the time. What is the average number of machine cycles per instruction for this microprocessor, including its memory fetch instructions?
On a uniprocessor, portion A of program P consumes 24 seconds, while portion B consumes 822 seconds. On a parallel computer, moderately serial portion A speeds up 4 times, while perfectly parallel portion B speeds up by the number of processors. 1- What is the speedup of program P on 1,024 processors? _______ times 2- How many processors are required to achieve at least half the theoretical maximum possible speedup on P?
Assume for a given program, 60% of the executed instructionsare of Class A, 10% are of Class B, and 30% are of Class C. Furthermore,assume that an instruction in Class A requires 3 cycles, an instruction inClass B requires 2 cycles, and an instruction in Class C requires 2 tocomplete. i. Compute the overall CPI for this program.ii. Compute the clock rate of the CPU when the time it takes tocomplete 20 instructions is 1.73 ???????????
Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?
Suppose that the processor has access to two levels of memory. Level 1 contains 1000 data words and has an access time between the CPU and L1 of 2.5 nanoseconds (2.5E-9 sec); level 2 contains data 100,000 words and has an access time between L1 and L2 transfers of 5.0 nanoseconds (5.0E-9 sec) Assume that data requests by the CPU have a hit ratio, H in the L1 cascade of 0.7, and any requests missed in L! Are guaranteed to be found in L2. What is the average memory assess time in nanoseconds for data requests by the CPU?
Suppose that a computer has a processor with two L1 caches, one for instructions and one for data, and an L2 cache. Let τ be the access time for the two L1 caches. Themiss penalties are approximately 15τ for transferring a block from L2 to L1, and 100τ fortransferring a block from the main memory to L2. For the purpose of this problem, assumethat the hit rates are the same for instructions and data and that the hit rates in the L1 andL2 caches are 0.96 and 0.80, respectively.(a) What fraction of accesses miss in both the L1 and L2 caches, thus requiring accessto the main memory?(b) What is the average access time as seen by the processor?(c) Consider the following change to the memory hierarchy. The L2 cache is removedand the size of the L1 caches is increased so that their miss rate is cut in half. Whatis the average memory access time as seen by the processor in this case
Suppose a processor has access to three levels of memory. Level 1 has an access timeof 9 microseconds, level 2 has an access time of 23 microseconds and level 3 has anaccess time of 65 microseconds. Level 1 contains a subset of the bytes contained inlevel 2, and level 2 contains a subset of the bytes contained in level 3. It is estimatedthat 35 % of all requested bytes are contained in level 1, 68 % of all requested bytesare contained in level 2 and 100 % of all requested bytes are contained in level 3. If abyte to be accessed is in level 1, then the processor will directly access it from level 1.If a byte to be accessed is not in level 1 but in level 2, then the processor will directlyaccess it from level 2. If a byte to be accessed is not in level 1 and not in level 2, thenthe processor will directly access it from level 3. For simplicity, we assume that theaccessed bytes are not transferred between the memory levels. Moreover, we ignorethe time that is required for the processor to…