Number 2 cse .part 2 ,sir please solve this for me.it will be a great help ,you can solve it in a page Suppose we have a memory and a 2-way set-associativecache with the following characteristics.Memory is byte addressable. Memory addresses are 16 bits.The cache has 64 lines and each cache line holds 8 bytes ofdata(a) Show the memory address formatMemory address(b) Given a sequence of four binary memoryaddresses in the order they are used to reference d070 1101 1011 001memory, indicate whether that reference is a hitor a miss. Assume that the cache is initiallyempty.You need to show the calculation.0010 1101 1@11 10000110 1101 1011 0111ara 1101 1011 1000

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Suppose we have a memory and a 2-way set-associative cache with the following characteristics. Memory is byte addressable. Memory addresses are 16 bits. The cache has 64 lines and each cache line holds 8 bytes of data (a) Show the memory address formati Memory address (b) Given a sequence of four binary memory addresses in the order they are used to reference d070 1101 I011 001 memory, indicate whether that reference is a hit or a miss. Assume that the cache is initially empty. You need to show the calculation. 0010 1101 1011 1000 0110 1101 1011 0111 iara 1101 1011 1000

Suppose we have a memory and a 2-way set-associative cache with the following characteristics. Memory is byte addressable. Memory addresses are 16 bits. The cache has 64 lines and each cache line holds 8 bytes of data (a) Show the memory address formati Memory address (b) Given a sequence of four binary memory addresses in the order they are used to reference d070 1101 I011 001 memory, indicate whether that reference is a hit or a miss. Assume that the cache is initially empty. You need to show the calculation. 0010 1101 1011 1000 0110 1101 1011 0111 iara 1101 1011 1000

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Now, we consider a 16-byte, four-way, fully-associative cache. Since the capacity of the cache is 16 bytes, the array "a" in our example (does/does not) fit inside the cache. We can deduce that the block size for this cache is ( ？ ) bytes per block. So the block index size b=2 bits. For a memory trace record such as: L 1fff000116,2 the 2-bit block offset is (0b01/0b10/0b11/0b00). The tag bits are all the rest of the bits not part of the block offset.
A cache memory has a line size of eight 64-bit words and a capacity of 4K words. The main memory size that is cacheable is 1024 Mbits. Assuming 4-way set associative mapping and that the addressing is done at the byte level. What is the format of the main memory addresses (i.e s-d, d, and w)? For the hexadecimal main memory location 2BFACEDH, find the corresponding 4-way set-associative memory format
Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?
Suppose a computer using direct-mapped cache has 232 (that's 232)232) bytes of byte-addressable main memory, and a cache size of 512 bytes, and each cache block contains 64 bytes. How many blocks of main memory are there? What is the format of a memory address as seen by cache, i.e. what are the sizes of the tag, block, and offset fields? To which cache block will the memory address 0x13A4498A map?
Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
Consider a computer with 128 MB of main memory, 64 KB of cache, and 4 bytes per memory block. Find out how to split the address (s-r, r, w) so that it can be used for direct mapping.Find out how to split the address into two parts (s and w) for associative mapping.Find out how to split the address into three parts (s-d, d, and w) for set associative mapping. Assume that each cache set has two lines.
Take into account the following scenario: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Since there are 8 bytes in a block, you can use that information to calculate how big the offset field has to be.
Let's pretend for a moment that we have a byte-addressable computer with fully associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. The following holds true if each block is 16 bits in size:a) Determine how many bytes the offset field is.Measure the tag field's width and height in pixels (b).
Suppose a byte-addressable computer using set associative cache has 224 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Suppose we have a system with the following properties:The memory is byte addressable.Memory accesses are to 1-byte words (not to 4-byte words).Addresses are 12 bits wide.The cache is two-way set associative (E = 2), with a 4-byte blocksize (B = 4) and four sets (S = 4).
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