The entity declaration for the counter is: entity binary_counter is generic (n: integer := 4); port ( clk : in std_logic; cnten in std_logic; rst bar in std_logic; -- -- generic for counter width system clock -- enable counter count -- synchronous reset (active low) q out std_logic_vector (n-1 downto 0)); -- output end binary_counter; The alternative architectures for the counter must all be written in behavioral style. The four alter- native versions of the architecture are based on using either a variable or signal to store the count in the counter's description. One architecture must use an unsigned variable, one must use an unsigned signal, one must use integer variable, and one must use an integer signal. Write the four design descriptions for the counter. With the generic set to 4, use stimulators to verify the counter's operation for each design. Use a clock period of 100 ns for clk. Change the generic to 6 and verify that each of your descriptions gives you a 6-bit binary counter.

Using a combination of shift registers and latches explain how a small number ofmicrocontroller I/O pins can be used to read from or write to a large number of digitalsignal lines. Illustrate your answer. What is the main disadvantage of this I/O expansionapproach?

4. MOS combining both P- and N-channel in series is called 5. The CMOS logic levels are: binary 0 = volts and binary 1 = volts.