use IEEE.STD_LOGIC_1164.ALL; entity GCC is Port ( systemClock, reset : in STD_LOGIC; stateOutput : out STD_LOGIC_VECTOR (4 downto 0)); end GCC; architecture Behavioral of GCC is component FreqDivider is Port (systemClock : in STD_LOGIC; slowClock : out STD_LOGIC); end component; signal nextState, presentState: std_logic_vector(5 downto 0) := "00000"; signal slowClock: std_logic;

Draw a circuit schematic for the following RTL circuit description st : R1 ← R1 + R3, R2 ← R2 +1 st: R30 st: R3 R1, R2 ← R1 st: R3 R2 + R3

Figure Q7 describes a Linear Feedback Shift Register (LFSR). Draw the equivalent schematic diagram of the system based on an off-the-shelf shift register, clearly showing the number of exclusive-OR gates needed to construct it. LIBRARY ieee; USE ieee.std logic_1164.all; entity lfsr is CLK, RESET: in STD LOGIC; Q: out STD LOGIC_VECTOR (5 downto 0) ); port ( end lfsr; architecture behavior of lfsr is begin process (CLK,RESET) begin if RESET='1' then Q <= "000001"; else Q <= ( Q(3) xor Q(2) xor Q(0) ) & Q(5 downto 1); end if; end process; end behavior;

What kinds of problems are suitable for solution by systolic arrays?

Compile the RISC-V assembly code for the following C code.

Assume we are writing a testbench for a sequential circuit that has three control inputs (cA, cB, cC) and a periodic clock (clk). If we define CLK_PERIOD as a localparameter with a value of 50 (nsec), write the testbench segment that would ensure all possible combinations of the control inputs were tested on a clock rising edge. This is can be done more elegantly if you define each time step in terms of the constant CLK_PERIOD. Your answer should include the statements that define clk, cA, cB, and cC over time. Hint: think of how you would show all combinations of three variables on a truth table and replicate that over time, where each combination is held over a timespan with a clock triggering edge.

Design the interface for a positive logic switch to TM4C123GXL Port A pin 7. Show formulas and calculations for each circuit element. Draw the circuit schematics with components labelled with their names and values. Write the C code as a function to initialize the port for interfacing the switch. Write a function to read the data value of Port A pin 7. Comment your code to explain each initialization step clearly.

Given the these minterms (4, 5, 6, 7, 8, 9, 10, 13, 14, 15), write a VHDL STATEMAENT for the function as a SOP. Please use this Entity Declaration in formulating the statement entity midterm is Port(A, B, C, D in STD_LOGIC; F: out STD_LOGIC); end midterm;

When a datapath was implemented, it only allowed for the register addressing mode. Which link in the data pipeline is unnecessary here?

Demonstrate in CXprogrammer with CPH1 device type the SCL3 command using BCD inputs of 3-15 and producing an output current of 4-20 mA.