What are the answers for following questions? i)“Using sll instruction to multiply numbers by multiples of 2” is mostly used in _______ operations. ii)Instruction memory, inside of MIPS, is a combination element. True / False iii) ___________ architecture implies, arithmetic and logic operations can only take place between CPU registers.

What are the answers for following questions? i)“Using sll instruction to multiply numbers by multiples of 2” is mostly used in _ operations. ii)Instruction memory, inside of MIPS, is a combination element. True / False iii) _____ architecture implies, arithmetic and logic operations can only take place between CPU registers.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 10RQ: How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency...

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What are the answers for these questions? i)___________ architecture implies, arithmetic and logic operations can only take place between CPU registers. ii) Instruction memory, inside of MIPS, is a combination element. True / False iii)“Using sll instruction to multiply numbers by multiples of 2” is mostly used in _______ operations.
2- Show how each of the following MIPS instructions is converted into machine code. Assume the memory address of the first instruction is 100 hex. addi $t0, $Zero, -50 andi $t1, $t0, 7 Loop:and $t1,$t0,$t1 Sw $t0, 40 ($t1) Bne $t1,$ zero, Loop Please show all the steps... and explain how you are getting the answer, thank you in advance!
a)Analyse and elaborate the factors affecting the choice of instruction length in aprocessor. b)A processor is able to perform a variable length instruction. It can performTHREE (3) different instruction length modes as follows:• instructions with two 15-bit addresses and one 3-bit register number• instructions with one 15-bit address and one 3-bit register number• instructions with no addresses or registersDesign a variable-length opcode to allow all the instruction to be encoded in a 36-bit instruction. Justify your answer. c)Briefly define the following terms:(i) instruction-level parallelism(ii) true data dependency(iii) procedural dependency(iv) resource conflicts
Assume the following register contents: $t0 = 0x01234567, $t1 = 0x56781234. Set back to these values back after answering each question. For the register values shown above, what is the value of registers ($t0, $t1, $t2, $t3) after executing each instruction? sll $t2, $t0, 2 and $t3, $t2, $t1
(a) Write the Assembly language instruction to move value 1234H into register BX.(b) Write the Assembly language instructions to add the values 16H and ABH. Place the result inregister AX.(c) No value can be moved directly into which registers ?(d) What is the largest hex value that can be moved into a 16-bit register ? Into an 8-bit register ? Whatare the decimal equivalents of these hex values ?
Assume that registers $s0 and $s1 hold the values 0x90000000 and 0xA0000000, respectively. These are integer values. Please take into account that these are 32-bit registers. a) What is the value of $t0 after the following MIPS instruction has been completed? add $t0, $s0, $s1 $s0: 0 x 9 0 0 0 0 0 0 0 $s1: 0 x A 0 0 0 0 0 0 0
Please answer this question and provide the explanation Assume the values of %ecx is 0x00000005 and %edx is 0x00000003. What would be the value of %ecx and %edx after performing the following instruction? 0x5555555461a <+0>: leal (%ecx, %edx, 8), %edx %ecx = 0x00000005, %edx = 0x0000003A %ecx = 0x00000005, %edx = 0x00000018 %ecx = 0x00000005, %edx = 0x00000030 %ecx = 0x00000005, %edx = 0x00000003 %ecx = 0x00000005, %edx = 0x0000001D %ecx = 0x00000005, %edx = 0x00000040 %ecx = 0x00000055, %edx = 0x0000001D %ecx = 0x00000005, %edx = 0x0000002A %ecx = 0x00000005, %edx = 0x00000025 %ecx = 0x00000005, %edx = 0x00000035
We want to build a byte organized main memory of 8 GB for a 32-bit CPU architecture composed ofbyte organized memory modules of 30-bit address and 8-bit data buses each.a) Draw the interface of the main memory by clearly indicating the widths of the buses.b) How many memory modules would be necessary to build the memory system?c) Design the main memory internal organization built out of the above memory modules (usemultiplexers and/or decoders as needed) by clearly indicating the widths of the used bussesd) Can we use this memory system as RAM for the CPU in Problem 1? Explain your answer.
Q 1. Answer the following short questions. Support your answers with diagram, where needed: How the LIFO memory differs to FIFO Memory. Which type of addressing mode is used by the Instruction: ADD [BX+2], AX? What is the equivalent of a Binary number: 00110100011012 in octal and hexa-decimal. How much memory space is addressable (in bytes) by a microprocessor, if it uses 36 address lines? If Base address = A000H, Physical address = A0345H, then the offset add = ___________? Why address bus is unidirectional and data bus is bidirectional in 8086?
How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?
More registers appear to be a good thing, in terms of reducing the total number of memory accesses a program might require. Give an arithmetic example to support this statement. First, determine the number of memory accesses necessary using MARIE and the two registers for holding memory data values (AC and MBR). Then perform the same arithmetic computation for a processor that has more than three registers to hold memory data values.
The purpose of adding cache between main memory and CPU is ( ).A. Solve the speed matching problem between CPU and main memory. Increase the capacity of the main memory.C. Enlarging the number of general-purpose registers in the CPU D. Both increasing the main memory capacity and increasing the number of general-purpose CPU registers