write verilog code for huffman encoder and decoder and draw the RTL or block diagram for huffman encoder and decoder

In Experiment #5, the enable line is used to obtain a 3-to-8 decoder using two 2-to-4 decoders. Design by showing a block diagram schematic (not a logic diagram); a 5-to-32 decoder using only 2-to-4 decoders and 3-to-8 decoders like the ones shown in the figures below. Each enabler (EN) must be assigned. 2 to 4 Y2 Ao Decoder Y1 Yo

2- For the signal x(t) of Figure(1), Use MATLAB or python to plot: a. 4x(-1/4) b. x(t-6) c. 2x(2t-1) d.-4x(t-2) J(0)4

you need to design and draw a 3-bit synchronous binary up/down counter for experiment 5. You need to add a bit named "M" for the excitation table that helps it switch between up and down mode and draw the state transition diagram, excitation table, k-map and circuit diagram with T-flip flops. When M = 0, it will perform up counter. When M = 1, it will perform down counter.