Computer Science: An Overview (13th Edition) (What's New in Computer Science)
13th Edition
ISBN: 9780134875460
Author: Glenn Brookshear, Dennis Brylow
Publisher: PEARSON
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Textbook Question
Chapter 2.7, Problem 1QE
Referring back to Questions 3 of Section 2.3, if the machine used the pipeline technique discussed in the text, what will be in “the pipe” when the instruction at address 0xAA is executed? Under what conditions would pipelining not prove beneficial at this point in the program?
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Yes, even if pipeline instructions take a different amount of time to execute at different times. Where can the problems with this situation be found?
If the execution times of the pipeline instructions are not balanced, is pipelined execution still possible? Where do you see the inefficiencies here?
Question 7: Suppose in a program there are 300 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the efficiency of pipeline parallel processing.
Chapter 2 Solutions
Computer Science: An Overview (13th Edition) (What's New in Computer Science)
Ch. 2.1 - What sequence of events do you think would be...Ch. 2.1 - What information must the CPU supply to the main...Ch. 2.1 - Prob. 3QECh. 2.2 - Prob. 1QECh. 2.2 - In the text, JUMP instructions were expressed by...Ch. 2.2 - Is the instruction If 0 equals 0, then jump to...Ch. 2.2 - Write the example program in Figure 2.7 in actual...Ch. 2.2 - The following are instructions written in Vole...Ch. 2.2 - What is the difference between the instructions...Ch. 2.2 - Here are some instructions in English. Translate...
Ch. 2.3 - Prob. 1QECh. 2.3 - Suppose the Vole memory cells at addresses 0xB0 to...Ch. 2.3 - Suppose the Vole memory cells at addresses 0xA4 to...Ch. 2.3 - Suppose the Vole memory cells at addresses 0xF0 to...Ch. 2.4 - Prob. 1QECh. 2.4 - Prob. 2QECh. 2.4 - Prob. 3QECh. 2.4 - a. Suppose you XOR the first 2 bits of a string of...Ch. 2.4 - Prob. 5QECh. 2.4 - Prob. 6QECh. 2.4 - Prob. 7QECh. 2.4 - Prob. 8QECh. 2.4 - Prob. 9QECh. 2.4 - Prob. 10QECh. 2.4 - Using Vole machine language (Appendix C), write a...Ch. 2.4 - Prob. 12QECh. 2.5 - Prob. 1QECh. 2.5 - Prob. 2QECh. 2.5 - Prob. 3QECh. 2.6 - The hypotenuse example script truncates the sides...Ch. 2.6 - Prob. 2QECh. 2.6 - The Python built-in function str () will convert a...Ch. 2.6 - Use the Python built-in bin () to write a script...Ch. 2.6 - Prob. 6QECh. 2.7 - Referring back to Questions 3 of Section 2.3, if...Ch. 2.7 - Prob. 2QECh. 2.7 - Suppose there were two central processing units...Ch. 2 - a. In what way are general-purpose registers and...Ch. 2 - Answer the following questions in Vole machine...Ch. 2 - Prob. 3CRPCh. 2 - What is the value of the program counter in the...Ch. 2 - Prob. 5CRPCh. 2 - Prob. 6CRPCh. 2 - Prob. 7CRPCh. 2 - Suppose a machine language is designed with an...Ch. 2 - Translate the following instructions from English...Ch. 2 - Rewrite the program in Figure 2.7 assuming that...Ch. 2 - Classify each of the following Vole instructions...Ch. 2 - Prob. 12CRPCh. 2 - Prob. 13CRPCh. 2 - Suppose the memory cells at addresses 0x00 through...Ch. 2 - Suppose the memory cells at addresses 0x00 through...Ch. 2 - Suppose the memory cells at addresses 0x00 through...Ch. 2 - Suppose the memory cells at addresses 0x00 through...Ch. 2 - Prob. 18CRPCh. 2 - If the Vole executes an instruction every...Ch. 2 - Prob. 20CRPCh. 2 - Prob. 21CRPCh. 2 - Prob. 22CRPCh. 2 - Prob. 23CRPCh. 2 - Write a program in Vole to compute the sum of...Ch. 2 - Prob. 26CRPCh. 2 - Prob. 27CRPCh. 2 - Suppose the following program, written in Vole, is...Ch. 2 - Summarize the steps involved when the Vole...Ch. 2 - Summarize the steps involved when the Vole...Ch. 2 - Summarize the steps involved when the Vole...Ch. 2 - Suppose the registers 0x4 and 0x5 in the Vole...Ch. 2 - Prob. 33CRPCh. 2 - Prob. 34CRPCh. 2 - Prob. 35CRPCh. 2 - Prob. 36CRPCh. 2 - Prob. 37CRPCh. 2 - Prob. 38CRPCh. 2 - Prob. 39CRPCh. 2 - Prob. 40CRPCh. 2 - Prob. 41CRPCh. 2 - Prob. 42CRPCh. 2 - a. What single instruction in the Vole machine...Ch. 2 - Write a Vole program that reverses the contents of...Ch. 2 - Write a Vole program that subtracts the value...Ch. 2 - Prob. 46CRPCh. 2 - Suppose a person is typing forty words per minute...Ch. 2 - Prob. 48CRPCh. 2 - Suppose the Vole communicates with a printer using...Ch. 2 - Write a Vole program that places 0s in all the...Ch. 2 - Prob. 51CRPCh. 2 - Prob. 52CRPCh. 2 - Suppose you are given 32 processors, each capable...Ch. 2 - Prob. 54CRPCh. 2 - Prob. 55CRPCh. 2 - Describe how the average of a collection of...Ch. 2 - Write and test a Python script that reads in a...Ch. 2 - Write and test a Python script that reads in a...Ch. 2 - Prob. 59CRPCh. 2 - Suppose a computer manufacturer develops a new...Ch. 2 - Prob. 2SICh. 2 - Prob. 3SICh. 2 - Prob. 4SICh. 2 - Suppose a manufacturer produces a computer chip...Ch. 2 - Prob. 6SICh. 2 - Prob. 7SICh. 2 - Prob. 8SI
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- If the execution time of pipeline instruction execution is not balanced, what inefficiency must be introduced to allow the piplelined execution to occur? Describe this inefficiency.arrow_forwardWhat would occur if an instruction were to be disregarded? A software-managed TLB is quicker than a hardware-managed TLB in the following situations:arrow_forwardThe answer to this question is still "yes," even if the time required to execute pipeline instructions differs. Is there a way to recognize the flaws in this plan of action?arrow_forward
- Using graphical representation to show the forwarding technique cannot completely avoid the data hazard. How many stall cycles are there when the forwarding technique is used? What is the advantage of having the source register fields in a fixed location for each instruction in instruction pipeline design?arrow_forwardEven if the execution time of pipeline instructions varies, the answer to this query remains affirmative. Exists a location where the issues with this scenario can be observed?arrow_forwardWhat would happen if an instruction was disobeyed, and why would that be the case? In the following scenarios, a TLB that is maintained by software is more efficient than one that is handled by hardware:arrow_forward
- Is it possible to achieve piplelined execution if the execution time of pipeline instruction execution is not balanced? What inefficiency do you see here?arrow_forwardWhat does "instruction pipelinelining" really mean? Give the answers as well as a description of the branch conflicts and data discrepancies.arrow_forwardDescribe the concept of instruction pipelining in a CPU. What are hazards in pipelining, and how can they be resolved?arrow_forward
- Even if the time it takes to execute pipeline instructions varies, the answer to this question is still yes. Is there a place where the problems with this scenario may be seen?arrow_forwardWhat is instruction pipelining? Explain the data conflicts and branch conflictsalong with is remedies.arrow_forwardQuestion 3 Assuming a program with no branch instructions but with a lot of memory access instructions, will this new pipeline harm performance? (Y/N) Please detailed explanation Full explain this question and text typing work only Don't copy and paste before solutionarrow_forward
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