Chapter 5, Problem 5.7.6E

Explanation of Solution

Given:

Processor speed = $\text{2GHz}$

Main memory access time = $\text{100ns}$

First-level cache miss rate = $\text{7\%}$

Second-level cache = $\text{12 cycles}$

Second-level cache miss rate = $\text{3}\text{.5\%}$

Second-level hit = $\text{50 cycles}$

Base CPI = $\text{1}\text{.5}$

Second-level 8-way set associative access = $\text{28 cycles}$

Global miss rate with second-level 8-way set associative access = $\text{1}\text{.5\%}$

Second-level miss rate = $\text{4\% - 0}\text{.7\%}$

Calculation:

Second-level direct-mapped on chip cache:

$\begin{array}{l}\text{Memory miss cost = Processor speed + Main memory access}\\ \text{ = }\left(\text{2 }\times {\text{ 10}}^9\right)\times \left(\text{100 }\times {\text{ 10}}^{-9}\right)\\ \text{ = 200 cycles}\end{array}$

$\begin{array}{l}\text{Total CPI = }\left(\text{Base CPI}\right)\text{ + }\left(\text{second level cache }\times \text{ first level miss rate}\right)\text{ +}\\ \left(\text{memory miss cost × Second-level cache miss rate}\right)\\ \text{ = 1}\text{.5 + }\left(\text{12 }\times \text{ 7\%}\right)\text{ + }\left(\text{200 }\times \text{ 3}\text{.5\%}\right)\\ \text{ = 1}\text{.5 + }\left(\text{12 }\times \text{ 0}\text{.07}\right)\text{ + }\left(\text{200 }\times \text{ 0}\text{.035}\right)\\ \text{ = 1}\text{.5 + 0}\text{.84 + 7}\\ \text{ = 9}\text{.34}\end{array}$

External memory:

$\begin{array}{l}\text{Total CPI = }\left(\text{Base CPI}\right)\text{ + }\left(\text{first-level miss per instruction × second-level hit}\right)\\ \text{ × }\left(\text{main memory access cycles}\right)\\ \text{ 9}\text{.34 = 1}\text{.5 + }\left(\text{0}\text{.7\% × 50}\right)\text{ + }\left(\text{200}\right)\left(\text{4\% }-\text{ 0}\text{.7n\%}\right)\\ \text{9}\text{.34 }-\text{ 1}\text{.5 = }\left(\text{0}\text{.07 × 50}\right)\text{ + }\left(\text{200}\right)\left(\text{0}\text{.04 }-\text{ 0}\text{.007n}\right)\\ \text{ 7}\text{.84 = 3}\text{.5 + 200}\left(\text{0}\text{.04 }-\text{ 0}\text{.007n}\right)\\ \text{7}\text{.84 }-\text{3}\text{.5 = 200}\left(\text{0}\text{.04 }-\text{ 0}\text{.007n}\right)\\ 4.34\text{ = 200}\left(\text{0}\text{.04 }-\text{ 0}\text{.007n}\right)\\ \frac{\text{ 4}\text{.34}}{200}\text{ = 0}\text{.04 }-\text{ 0}\text{.007n }\end{array}$

$\begin{array}{l}0.0217\text{ = 0}\text{.04 }-\text{ 0}\text{.007n}\\ 0.0217-\text{ 0}\text{.04 = }-\text{0}\text{.007n}\\ -\text{0}\text{.0183 = }-\text{0}\text{.007n}\\ \text{ n = }\frac{\text{0}\text{.0183}}{0.007}\\ \text{ n = 2}\text{.61}\end{array}$

Therefore, the second-level direct-mapped on chip cache is “$2.61$”.

Second-level 8-way set associative cache:

$\begin{array}{l}\text{Memory miss cost = Processor speed + Main memory access}\\ \text{ = }\left(\text{2 }\times {\text{ 10}}^9\right)\times \left(\text{100 }\times {\text{ 10}}^{-9}\right)\\ \text{ = 200 cycles}\end{array}$

$\begin{array}{l}\text{Total CPI = }\left(\text{Base CPI}\right)\text{ + }\left(\text{Second-level 8-way set associative access × first level miss rate}\right)\text{ +}\\ \left(\text{memory miss cost × Global miss rate with second-level 8-way set associative access}\right)\\ \text{ = 1}\text{.5 + }\left(\text{28 × 7\%}\right)\text{ + }\left(\text{200 × 1}\text{.5\%}\right)\\ \text{ = 1}\text{.5 + }\left(\text{28 × 0}\text{.07}\right)\text{ + }\left(\text{200 × 0}\text{.015}\right)\\ \text{ = 1}\text{.5 + 1}\text{.96 + 3}\\ \text{ = 6}\text{.46}\end{array}$

External memory:

$\begin{array}{l}\text{Total CPI = }\left(\text{Base CPI}\right)\text{ + }\left(\text{first-level miss per instruction × second-level hit}\right)\\ \text{ × }\left(\text{main memory access cycles}\right)\\ \text{ 6}\text{.46 = 1}\text{.5 + }\left(\text{0}\text{.7\% × 50}\right)\text{ + }\left(\text{200}\right)\left(\text{4\% }-\text{ 0}\text{.7n\%}\right)\\ \text{6}\text{.46 }-\text{ 1}\text{.5 = }\left(\text{0}\text{.07 × 50}\right)\text{ + }\left(\text{200}\right)\left(\text{0}\text{.04 }-\text{ 0}\text{.007n}\right)\\ \text{ 4}\text{.96 = 3}\text{.5 + 200}\left(\text{0}\text{.04 }-\text{ 0}\text{.007n}\right)\\ \text{4}\text{.96 }-\text{ 3}\text{.5 = 200}\left(\text{0}\text{.04 }-\text{ 0}\text{.007n}\right)\\ 1.46\text{ = 200}\left(\text{0}\text{.04 }-\text{ 0}\text{.007n}\right)\\ \frac{\text{ 1}\text{.46}}{200}\text{ = 0}\text{.04 }-\text{ 0}\text{.007n}\end{array}$

$\begin{array}{l}0.0073\text{ = 0}\text{.04 }-\text{ 0}\text{.007n}\\ 0.0073-\text{ 0}\text{.04 = }-\text{0}\text{.007n}\\ -\text{0}\text{.0327 = }-\text{0}\text{.007n}\\ \text{ n = }\frac{\text{0}\text{.0327}}{0.007}\\ \text{ n = 4}\text{.67}\end{array}$

Therefore, the second-level 8-way set associative cache is “$4.67$”.