Given Information : The following matrix transpose routine is given: //array declaration typedef int array[4][4]; //function to transpose array void transpose2(array dst, array src) { //variable declaration int i,j; //iterate through first array for(i=0;i<4;i++) { //iterate through second array for(j=0;j<4;j++) { //transpose matrix dst[j][i]=src[i][j]; } } } The machine that runs the code has the following properties: The size of integer is “4”. The “src” array starts at address “0” and “dst” array starts at address “64”. There is a single L1 data cache that is direct-mapped, write-through and write allocate with a block size of 16 bytes. The cache has a total size of “32” bytes and the cache is initially empty. The only sources of read and write misses are accesses to the “src” and “dst” array.

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Answer 1

Question

Chapter 6, Problem 6.34HW

Program Plan Intro

Given Information:

The following matrix transpose routine is given:

//array declaration

typedef int array[4][4];

//function to transpose array

void transpose2(array dst, array src)

{

//variable declaration

int i,j;

//iterate through first array

for(i=0;i<4;i++)

{

//iterate through second array

for(j=0;j<4;j++)

{

//transpose matrix

dst[j][i]=src[i][j];

}

}

}

The machine that runs the code has the following properties:

The size of integer is “4”.

The “src” array starts at address “0” and “dst” array starts at address “64”.

There is a single L1 data cache that is direct-mapped, write-through and write allocate with a block size of 16 bytes.

The cache has a total size of “32” bytes and the cache is initially empty.

The only sources of read and write misses are accesses to the “src” and “dst” array.

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Answer 2

Question

Chapter 6, Problem 6.34HW

Program Plan Intro

Given Information:

The following matrix transpose routine is given:

//array declaration

typedef int array[4][4];

//function to transpose array

void transpose2(array dst, array src)

{

//variable declaration

int i,j;

//iterate through first array

for(i=0;i<4;i++)

{

//iterate through second array

for(j=0;j<4;j++)

{

//transpose matrix

dst[j][i]=src[i][j];

}

}

}

The machine that runs the code has the following properties:

The size of integer is “4”.

The “src” array starts at address “0” and “dst” array starts at address “64”.

There is a single L1 data cache that is direct-mapped, write-through and write allocate with a block size of 16 bytes.

The cache has a total size of “32” bytes and the cache is initially empty.

The only sources of read and write misses are accesses to the “src” and “dst” array.

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Answer 3

Question

Chapter 6, Problem 6.34HW

Program Plan Intro

Given Information:

The following matrix transpose routine is given:

//array declaration

typedef int array[4][4];

//function to transpose array

void transpose2(array dst, array src)

{

//variable declaration

int i,j;

//iterate through first array

for(i=0;i<4;i++)

{

//iterate through second array

for(j=0;j<4;j++)

{

//transpose matrix

dst[j][i]=src[i][j];

}

}

}

The machine that runs the code has the following properties:

The size of integer is “4”.

The “src” array starts at address “0” and “dst” array starts at address “64”.

There is a single L1 data cache that is direct-mapped, write-through and write allocate with a block size of 16 bytes.

The cache has a total size of “32” bytes and the cache is initially empty.

The only sources of read and write misses are accesses to the “src” and “dst” array.

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Answer 4

Question

Chapter 6, Problem 6.34HW

Program Plan Intro

Given Information:

The following matrix transpose routine is given:

//array declaration

typedef int array[4][4];

//function to transpose array

void transpose2(array dst, array src)

{

//variable declaration

int i,j;

//iterate through first array

for(i=0;i<4;i++)

{

//iterate through second array

for(j=0;j<4;j++)

{

//transpose matrix

dst[j][i]=src[i][j];

}

}

}

The machine that runs the code has the following properties:

The size of integer is “4”.

The “src” array starts at address “0” and “dst” array starts at address “64”.

There is a single L1 data cache that is direct-mapped, write-through and write allocate with a block size of 16 bytes.

The cache has a total size of “32” bytes and the cache is initially empty.

The only sources of read and write misses are accesses to the “src” and “dst” array.

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Answer 5

Chapter 6, Problem 6.34HW

Program Plan Intro

Given Information:

The following matrix transpose routine is given:

//array declaration

typedef int array[4][4];

//function to transpose array

void transpose2(array dst, array src)

{

//variable declaration

int i,j;

//iterate through first array

for(i=0;i<4;i++)

{

//iterate through second array

for(j=0;j<4;j++)

{

//transpose matrix

dst[j][i]=src[i][j];

}

}

}

The machine that runs the code has the following properties:

The size of integer is “4”.

The “src” array starts at address “0” and “dst” array starts at address “64”.

There is a single L1 data cache that is direct-mapped, write-through and write allocate with a block size of 16 bytes.

The cache has a total size of “32” bytes and the cache is initially empty.

The only sources of read and write misses are accesses to the “src” and “dst” array.

Answer 6

Chapter 6, Problem 6.34HW

Program Plan Intro

Given Information:

The following matrix transpose routine is given:

//array declaration

typedef int array[4][4];

//function to transpose array

void transpose2(array dst, array src)

{

//variable declaration

int i,j;

//iterate through first array

for(i=0;i<4;i++)

{

//iterate through second array

for(j=0;j<4;j++)

{

//transpose matrix

dst[j][i]=src[i][j];

}

}

}

The machine that runs the code has the following properties:

The size of integer is “4”.

The “src” array starts at address “0” and “dst” array starts at address “64”.

There is a single L1 data cache that is direct-mapped, write-through and write allocate with a block size of 16 bytes.

The cache has a total size of “32” bytes and the cache is initially empty.

The only sources of read and write misses are accesses to the “src” and “dst” array.

Answer 7

Chapter 6, Problem 6.34HW

Program Plan Intro

Given Information:

The following matrix transpose routine is given:

//array declaration

typedef int array[4][4];

//function to transpose array

void transpose2(array dst, array src)

{

//variable declaration

int i,j;

//iterate through first array

for(i=0;i<4;i++)

{

//iterate through second array

for(j=0;j<4;j++)

{

//transpose matrix

dst[j][i]=src[i][j];

}

}

}

The machine that runs the code has the following properties:

The size of integer is “4”.

The “src” array starts at address “0” and “dst” array starts at address “64”.

There is a single L1 data cache that is direct-mapped, write-through and write allocate with a block size of 16 bytes.

The cache has a total size of “32” bytes and the cache is initially empty.

The only sources of read and write misses are accesses to the “src” and “dst” array.

Answer 8

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Answer 9

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Answer 10

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Answer 11

Ch. 6.1 - Prob. 6.1PP Ch. 6.1 - Prob. 6.2PP Ch. 6.1 - Prob. 6.3PP Ch. 6.1 - Prob. 6.4PP Ch. 6.1 - Prob. 6.5PP Ch. 6.1 - Prob. 6.6PP Ch. 6.2 - Prob. 6.7PP Ch. 6.2 - Prob. 6.8PP Ch. 6.4 - Prob. 6.9PP Ch. 6.4 - Prob. 6.10PP

Solution Summary: The author explains that each cache line is enough to hold one line of array and it here holds exactly one row of the array.

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Chapter 6 Solutions