PROGRAMMABLE LOGIC CONTROLLERS-ACCESS
5th Edition
ISBN: 9781259680915
Author: Petruzella
Publisher: MCG
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Chapter 7, Problem 6P
Program Plan Intro
Retentive Timer ON (RTO):
- RTO refers to an on-delay timer.
- RTO counts the time-based intervals as soon as the instruction becomes true.
- It retains the accumulated value as soon as instruction goes false or when power cycle occurs.
Explanation of Solution
b.
Required time:
- In “rung 2”and “rung 3”, the two RTO timers are interconnected.
- Here, the “present” value of “rung 2” is “2900” and the “present” value of “rung 3” is “1780”.
- Add these two present values to get the time required to produce the output.
- The sum of the two values is “4680”...
Explanation of Solution
c.
Conditions to be satisfied:
- The power required to be supplied to “L1” and close the input “PB1” contacts to turn the “rung 4” to “true”.
- Once, “PB1” becomes true, the “rung 2” star...
Explanation of Solution
d.
Status of the output:
- The RTO instruction used in the given diagram stores the timed count of timer and counts the time even if the power is lost or restored.
- The “rung 3” is required to activate the “DN” sign...
Explanation of Solution
e.
Result when PB2 is ON:
- If the input PB2 is “ON”, then the reset instructions of the timers “T4:1” and “T4:2” will make the “rung 1” as “true”...
Explanation of Solution
f.
Required accumulated time:
- The “rung 2” becomes “true” and the RTO instructions are started to execute when PB1 input contact is closed.
- The timer “T4:1” starts timing as long as the accumulated value attains the present value “2900”...
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Assume we are writing a testbench for a sequential circuit that has three control inputs (cA, cB, cC) and a periodic clock (clk). If we define CLK_PERIOD as a localparameter with a value of 50 (nsec), write the testbench segment that would ensure all possible combinations of the control inputs were tested on a clock rising edge. This is can be done more elegantly if you define each time step in terms of the constant CLK_PERIOD. Your answer should include the statements that define clk, cA, cB, and cC over time. Hint: think of how you would show all combinations of three variables on a truth table and replicate that over time, where each combination is held over a timespan with a clock triggering edge.
Draw a ladder logic diagram for the timer scenario shown.
Answer the following questions given the timing diagram of a certain flip-flop which has a clock of 10 MHz and a propagation delay time of 28 ns. Type letters only.
1. What is the type of triggering / clocking used?
A. Positive Level C. Positive Edge
B. Negative Level D. Negative Edge
2. What is the type of flip flop characterized by the timing diagram above?
A. RS NOR Latch C. JK Flip-flop
B. RS NAND Latch D. RS Flip-flop3. What is the actual input characterized by input “A”?
A. Input “R” C. Input “J”
B. Input “S” D. Input “K”
4. What is the actual input characterized by input “B”?
A. Input “R” C. Input “J”
B. Input “S” D. Input…
Chapter 7 Solutions
PROGRAMMABLE LOGIC CONTROLLERS-ACCESS
Ch. 7 - Prob. 1RQCh. 7 - Prob. 2RQCh. 7 - Prob. 3RQCh. 7 - Prob. 4RQCh. 7 - a. What are the two methods commonly used to...Ch. 7 - Prob. 6RQCh. 7 - Prob. 7RQCh. 7 - Prob. 8RQCh. 7 - For a TOF timer: a. When is the enable bit of a...Ch. 7 - Explain what each of the following quantities...
Ch. 7 - State the method used to reset the accumulated...Ch. 7 - Study the ladder logic program in Figure 7-40 and...Ch. 7 - Study the ladder logic program in Figure 7-42, and...Ch. 7 - Prob. 6PCh. 7 - Prob. 7PCh. 7 - Prob. 8PCh. 7 - Prob. 9PCh. 7 - Prob. 10PCh. 7 - Prob. 11PCh. 7 - Prob. 13PCh. 7 - When the lights are turned off in a building, an...
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